Книги+1 / 2013 [Chandan_Kumar_Sarkar]_Technology_CAD

FIGURE 8.4 (See color insert)

Placement of antimony dopant in the wafer after the application of drive-in voltage on it.

of SiO2 will be formed automatically by nature, which is needed to be etched out by the etch oxide all statement.

DIFFUSION TEMPERAT=800 T.FINAL=1200 TIME=100 F.O2=0.5 F.N2=9.5 DIFFUSION TEMPERAT=1200 TIME=600 F.O2=0.5 F.N2=9.5

DIFFUSION TEMPERAT=1200 T.FINAL=1000 TIME=67 F.O2=9 DIFFUSION TEMPERAT=1000 TIME=20 F.O2=10

DIFFUSION TEMPERAT=1000 TIME=67 F.O2=5.5 F.H2=10.4 DIFFUSION TEMPERAT=1000 TIME=1 F.O2=5.5 F.N2=5.0 DIFFUSION TEMPERAT=1000 T.FINAL=800 TIME=67 F.N2=10 etch oxide all

print layers

8.12  P-Type Epitaxial Growth

Drive-in voltage will place the NBL layer in proper place in the wafer. This N-layer in a P-type wafer will create a p-n junction that will stop high bottom leakage current flow due to high supply voltage at the drain end. To ensure this, both the initial wafer and buried layer are doped by boron and

FIGURE 8.5 (See color insert)

Placement of NBL and epitaxial growth on the initial wafer.

antimony of dose 1e15 cm–3, respectively. A p-n junction of the same depletion depth on both sides will be formed. For the actual structure an epitaxial layer of 14 μm is grown on this wafer, as device parameter optimization is possible in this epitaxial layer. It is always required to grow an epitaxial layer on the initial wafer, as shown in Figure 8.5, to avoid crystal defects in the initial wafer and parameter optimization is convenient in this epitaxial layer.

The statement epitaxy will create an epitaxial layer of 14 μm which will grow on this initial wafer [9–12], as stated below.

EPITAXY TIME=14 TEMPERAT=1150 THICKNES=14 dx =.001 ydy=0.0 SPACES=100 +

RESISTIV BORON=45 print layers

8.13  Pad Oxide Formation

During the masking process, as shown in Figure 8.6, the masking materials, nitride, and photoresist are not deposited directly on the wafer, as strain would be created on the wafer when the photoresist hardens due to ultraviolet (UV) light. This strain on the silicon material may change the property of the silicon material. So whenever this layer for masking is deposited, it is

FIGURE 8.6 (See color insert)

Pad oxide on the wafer is shown; here the y-axis has been chosen up to −12 μm.

always essential to grow a layer of oxide on the wafer to avoid strain. Hence, a layer of 500 A0 SiO2 has been grown here using the following statements.

DIFFUSION TEMPERAT=800 T.FINAL=900 TIME=10 F.O2=9.0 DIFFUSION TEMPERAT=900 TIME=15 F.O2=9.0

DIFFUSION TEMPERAT=900 TIME=18 F.O2=5.5 F.H2=10.4 DIFFUSION TEMPERAT=900 TIME=1 F.O2=5.5 F.N2=5.0 DIFFUSION TEMPERAT=900 TIME=10 F.N2=10

DIFFUSION TEMPERAT=900 T.FINAL=800 TIME=25 F.N2=10 print layers

8.14  Gate Under Channel Doping

Gate under substrate region is doped in this portion by boron of dose 2.0 e11cm–3. The mask chosen has been named ‘gateunderdoping’. Threshold voltage modification can be done by this doping. The statements needed to perform this doping procedure are given below. With the dose 2.0 e11cm–3, threshold voltage achieved is 0.65 V.

DEPOSIT PHOTORESIST NEGATIVE THICKNESS=1

EXPOSE MASK=gateunderdoping

376 Technology Computer Aided Design: Simulation for VLSI MOSFET

DEVELOP

etch nitride

etch oxide thickness=0.02

implant boron pearson tilt=7 dose=2.0e11 energy=100 etch nitride all

8.15  Gate Oxide Formation

For a MOS structure, gate oxide has to be formed. As gate length has been chosen 1.6 to 4.1 μm or effectively 2.5 μm, so the rest of the wafer has to be covered by mask, as shown in Figure 8.7. A mask has been assigned a length of 1600 to 4100 named gateoxet in mask file. As photoresist used here in most of the cases is the negative type, part of the length mentioned in the mask file will be dissolved when it is developed. Now the oxidation steps have been executed to form the gate oxide at the end of the oxidation steps. The entire photoresist and nitride will be removed from the remaining part of the wafer.

DIFFUSION TEMPERAT=800 T.FINAL=900 TIME=10 F.O2=0.25 F.N2=10 DIFFUSION TEMPERAT=900 TIME=5 F.O2=0.25 F.N2=10

DIFFUSION TEMPERAT=900 TIME=3 F.O2=9.5

DIFFUSION TEMPERAT=900 TIME=47.5 F.O2=9.5 F.HCL=0.19

FIGURE 8.7 (See color insert)

Structure of the wafer after formation of the gate oxide.

DIFFUSION TEMPERAT=900 TIME=3 F.O2=9.5

DIFFUSION TEMPERAT=900 TIME=15 F.N2=10.0

DIFFUSION TEMPERAT=900 T.FINAL=800 TIME=37.5 F.N2=10 print layers

etch Photoresist etch nitride all

8.16  Gate-Poly Deposition

MOS gate material may be polysilicon or metals [13]. As a gate metal, molybdenum or aluminum can be used. Polysilicon is polycrystalline silicon, a material consisting of small silicon crystals. Though polysilicon gate has severe disadvantages, such as low conductivity which can cause occurrence of delay in circuits as well as unwanted variation of threshold voltage of the MOSFET due to polysilicon depletion effect, polysilicon has several advantages over the metal gate. Polysilicon behaves like a perfect conductor once a poly-layer is doped properly, and it will reduce the delay in channel formation [14–17]. Typically doping concentrations are of the order of 1020 atoms cm–3. The main reason for use of the polysilicon gate is that fabrication processes require very high temperature annealing after the initial doping to passivate the radiation damage caused to the silicon crystal structure by the ion implantation [18– 19]. Metal gate would melt under such conditions, whereas polysilicon will not. Polysilicon needs a single-step process of etching, whereas a metal gate requires multiple steps. Threshold voltage of the MOSFET is corrected with the work function difference between the gate and the channel.

The statement below will deposit polysilicon on the entire wafer in the ambient temperature 625°C and pressure of 1.0 atmosphere. This statement also mentions the thickness of the deposited polysilicon material which is mentioned here as 0.4 μm. This polysilicon material will be used as polysilicon gate material of the MOSFET, as shown in Figure 8.8.

deposition polysili temperature=625 pressure=1.0 thickness=0.4 concentr

8.17  Polysilicon Gate Doping

Polysilicon doping is done by the following expression which is essential to increase the conductivity of the gate material.

DIFFUSION TEMPERAT=950 TIME=20 INERT

FIGURE 8.8 (See color insert)

Polysilicon material deposition on the grown gate oxide material.

8.18  Gate-Poly Mask

The polysilicon material is deposited on the entire wafer as shown in Figure 8.9. It is necessary to remove the unnecessary extra portion of polysilicon and oxide from the wafer. Here polysilicon is deposited on the total length of the gate oxide. So the same mask gateoxet has been called again, and the photoresist used here is a positive type so that from length 1600 to 4100 of the photoresist will remain on it and will use it as a mask for that portion. The remaining part of the photoresist will be dissolved when it is developed. This part nitride and polysilicon will be etched out by etch nitride and etch polysili statements. After the selective polysilicon etching, the remaining nitride will be removed using the etch nitride all statement. Figure 8.10 shows 2.5 μm polysilicon gate formation on the gate oxide.

DEPOSITION NITRIDE THICKNES=0.10 CONCENTR DEPOSIT PHOTORESIST POSITIVE THICKNESS=1 EXPOSE MASK=gateoxet

DEVELOP

etch nitride etch polysili etch nitride all

FIGURE 8.9 (See color insert)

Polysilicon gate formation on the gate oxide after selective polysilicon material by etching from the wafer; polysilicon gate length is 2.5 μm.

8.19  Creation of n+ Source and Drain Regions

The next step of fabrication is to create source and drain regions for the n-MOSFET, as shown in Figure 8.10. For n-type doping, arsenic dopant is used. The mask name used to mask the rest of the wafer is Nplus. Two lengths assigned in the Nplus mask are of lengths 900 to 1500 and 4200 to 4900. To cover the rest of the wafer top, it must be masked. So a negative photoresist has been deposited and mask name Nplus has been called, followed by the mask develop stage. From 0.9 to 1.5 μm and 4.2 to 4.9 μm there will not be any photoresist as the mask deposited was negative-type photoresist. Now the nitride and oxide materials from these portions will also be removed to implant arsenic in these regions for source/drain formation in the above-mentioned regions. Here arsenic of dose 6.0 e15 cm–3 with energy 100 keV has been doped in equal and opposite tilt 7° and –7° to get a source drain shape. After completion, source drain doping, photoresist, and nitride are removed from the entire wafer which was used as a mask at the time of source/drain doping.

DEPOSITION NITRIDE THICKNES=0.15 CONCENTR DEPOSIT PHOTORESIST NEGATIVE THICKNESS=1 EXPOSE MASK=Nplus

DEVELOP

etch nitride

FIGURE 8.10 (See color insert)

Device structure after source and drain formation.

etch oxide

implant arsenic pearson tilt=7 dose=6.0e15 energy=100 implant arsenic pearson tilt=-7 dose=6.0e15 energy=100 etch PHOTORESIST

etch nitride all

8.20  Creation of p+ Region

The next step is to create a p region that will remain connected to the substrate material and finally work as a bulk material. This p region mask length is chosen as 100 to 700, which means 0.1 to 0.7 μm, and the mask is named pplus. Figure 8.11 shows the formation of the p region that will be used as bulk material.

DEPOSITION NITRIDE THICKNES=0.15 CONCENTR DEPOSIT PHOTORESIST NEGATIVE THICKNESS=1 EXPOSE MASK=pplus

DEVELOP

etch nitride etch oxide

IMPLANT BORON PEARSON RP.EFF DOSE=1.0e15 ENERGY=30

Photoresist and nitride from the remaining part will be removed by etch photoresist and etch nitride all statements. Figure 8.12 shows the structure achieved

FIGURE 8.12 (See color insert)

The structure achieved by executions of etch photoresist and etch nitride all statements.

by executions of etch photoresist and etch nitride all statements. In this structure it is evident that bulk, source, and drain regions are formed by doping the wafer. Gate oxide and polysilicon deposition on the gate oxide are also being formed. The next step is to create metal contacts for the different regions for its terminals to connect the device with the outer world. To perform this next step, borophosphosilicate glass (BPSG) deposition and anneal are required. The diffusion statement causes annealing to occur. If the anneal occurs in an oxidizing ambient, then silicon oxidation will occur on the exposed silicon material surface. It is common to specify multiple anneal steps in sequence in order to accurately model a specific furnace process. Semiconductor material needs annealing after every ion implantation step. It will repair the damages caused in the lattice during ion bombardment by the collisions with doping ions. It also allows doping impurities to diffuse further into the bulk.

etch PHOTORESIST etch nitride all

8.21  Borophosphosilicate Glass (BPSG) Deposition

Borophosphosilicate glass (BPSG), shown in Figure 8.13, is important in the fabrication of silicon-based lightweight devices and integrated circuits [20]. It

FIGURE 8.13 (See color insert)

Borophosphosilicate glass deposition before the first layer of metal contact to the device.