Книги+1 / 2013 [Chandan_Kumar_Sarkar]_Technology_CAD

Therefore, by differentiating (7.100) as per the relationships (7.101) through (7.103), the various gate capacitances are determined as follows:

The fact that the capacitance CGB is zero at the strong inversion region may be explained by the fact that the inversion layer in the channel from the source to the drain screens the silicon bulk from the gate charge.

7.7.2.2  Intrinsic Capacitances in the Saturation Region

In the saturation region, the drain voltage is VDSsat, which is given by

VDSsat = VGS − VT, assuming long channel MOS transistor. Thus the gate-to- drain voltage becomes

Substituting (7.108) in (7.101), we get

Therefore, the various intrinsic gate capacitances in the saturation region are obtained as follows:

The physical explanation for (7.111) is the same as that provided for (7.106). The physical explanation for (7.110) is that in the saturation region the channel is pinched off, thereby the channel is electrically isolated from the drain. The gate charge is not influenced by the change in drain voltage, and thus the capacitance CGD vanishes.

7.7.2.3  Intrinsic Capacitances in the Subthreshold Region

In the subthreshold region, the inversion charge is negligible compared to the bulk depletion charge, so that the charge neutrality condition is given by

In (7.112), ψsa is the surface potential in the subthreshold region, which is given as [7]

Substituting (7.113) in (7.112) and performing an integration as done in (7.100), the total gate charge in the subthreshold region is given by

Therefore, by differentiating (7.114) as per the relationships (7.101) through (7.103), the various gate capacitances are determined as follows:

7.7.2.4  Intrinsic Capacitances in the Accumulation Region

In the accumulation region, VGS < VFB, the MOS structure behaves like a simple parallel plate capacitor and the capacitances are as follows:

7.7.2.5 Charge-Based Approach

It may be noted that Meyer’s approach for characterizing the intrinsic capacitances of a MOS transistor is simple and is widely used by the IC designers for first-hand estimation of the various MOS capacitances. However, this approach for characterization does not provide good results for some circuits such as MOS charge pump, static RAM, and switched capacitor circuits. Therefore, an alternative approach is used for characterizing the MOS capacitances in today’s compact models. This is the chargebased approach for capacitance characterization. In this approach, the

emphasis is put on the accurate characterization of charges of each terminals (QD ,QS ,QG ,QB ) of the MOS transistor. The calculation of total inversion charge in the channel is fairly easy. However, it is difficult to precisely characterize the charges on the source and the drain terminals. The inversion charge must be partitioned to the source and drain in a suitable manner. Several charge partitioning approaches have been suggested for the saturation region. They are 50/50, 40/60, and 0/100 and are distinguished in the compact models through a model parameter XPART = QD/QS as the charge partitioning ratio. The simplest way is to partition the channel charge and assign 50% of the inversion charge to the source and the rest

to the drain, which corresponds to (XPART = 0.5), which can be written as QS = QD = 0.5Qinv. When XPART > 0.5 , the 0/100 charge partitioning scheme is chosen which implies that QS = Qinv ,QD = 0 . When XPART < 0.5 , the 40/60 charge partitioning scheme is chosen. The 40/60 partition scheme, also

known as the Ward Dutton partitioning scheme [17], is physically correct as demonstrated through 2D device simulation results and experiments.

7.7.2.6  Effect of Poly-Silicon Gate Depletion Effect and

Finite Inversion Charge Layer Thickness

The poly-silicon gate depletion effect as discussed earlier needs to be considered while characterizing the intrinsic capacitances. This is implemented by replacing VGS in all model equations by VGS_ eff as defined in (7.74). The effect of finite inversion charge thickness can be characterized by a capacitance in series with the gate oxide capacitance Cox. This results in reduced effective gate oxide capacitance:

In (7.121), CC is the correction term added due to the inversion layer of thickness tinv.

7.7.3  Characterization of Extrinsic Capacitances

The extrinsic components of MOS transistor capacitances are categorized broadly into three types: (1) gate overlap capacitances in source/drain and

bulk region (CGSO/CGDO, CGSOL/CGDOL, CGBO); (2) inner and outer fringing capacitances (CFI and CFO); and (3) source/drain junction capacitances (CJS

and CJD). These capacitances at a given operating bias condition are required to be characterized.

7.7.3.1  Characterization of Fringing and Overlap Capacitances

Characterization of overlap capacitance in a MOS transistor device is especially important when the amount of overlap becomes significant compared

FIGURE 7.31

Overlap and fringing capacitances.

to the electrical channel length. As a crude estimate, the overlap capacitance is determined as follows [3]:

Here d is the amount of gate-to-drain/source overlap. However, when d is small, the fringing effect is significant. Let us consider the approximate structure, shown in Figure 7.31 for precise characterization of the overlap and fringing capacitances [18].

The overlap capacitance consists of the following three components: (1) outer fringing capacitance CFO between the gate and the source/drain, (2) direct overlap capacitance COV between the gate and the source/drain, and

(3) inner fringing capacitance CFI on the channel side between the gate and the side wall of the source/drain junction. These capacitances are calculated using conformal technique with appropriate boundary conditions [18]. These capacitances for unit width of the device are given as follows:

In (7.123), θ is the slope angle for the poly-silicon gate. For the vertical edge of the poly-silicon gate, θ = π/2. In (7.124), β is given by

In (7.125), is a correction factor to account for some higher-order effects and is given as follows:

The total overlap capacitance per unit width of the device is thus given by the sum of (7.123), (7.124), and (7.125).

In addition to the above overlap capacitances, there is another overlap capacitance in the channel width direction, which results in an overlap capacitance between the gate and the substrate. This is given as

Here in (7.128), CGBO′ is the gate-to-bulk overlap capacitance per unit length.

7.7.3.2  Characterization of Junction Capacitances

The junction capacitances arise from the depletion charge between the source or drain and the substrate. These are usually reverse-biased. Therefore, with the variation of source or drain voltages, the depletion charge increases or decreases accordingly. The depletion capacitance per unit area of an abrupt p-n junction is [5]

bias voltage across the junction. In (7.129), m is the grading coefficient and its

The junction capacitance has two components: bottom component and sidewall/perimeter component. The total junction capacitance is thus written as [3]

In (7.132), Cjb is the bottom component of the junction capacitance per unit area, A is the total junction area, Cjsw is the sidewall component of the junction capacitance per unit length, and P is the total junction perimeter. Using (7.131), the bottom component and perimeter component are defined as follows:

In (7.133), Cj0b is the zero-bias sidewall capacitance per unit area, and mb is the grading coefficient for the bottom component. In (7.134), Cj0sw is the zerobias sidewall capacitance per unit length, and msw is the grading coefficient for the sidewall.

7.7.4  Simulation Results and Discussion

The channel length is taken to be 65 nm and channel width is 10 μm. The oxide capacitance per unit area is 0.0197 F/m2. The simulation results include all sorts of extrinsic capacitances and intrinsic capacitances, which are calculated as per the charge-based approach. The charge partitioning ratio is taken to be 0, which means that 40/60 charge partitioning scheme has been considered. Here, we present an intuitive understanding of the graphs. This is important for VLSI designers.

The variations of gate-to-source capacitor CGS with VDS for three different values of VGS are shown in Figure 7.32. It is observed that in the subthreshold region, the gate-to-source capacitance value is very low. This can be explained by the fact that in the subthreshold region, the inversion charge is negligibly small. According to Meyer’s approach, CGS = 0 in the subthreshold region. However, there will be extrinsic components that contribute to this capacitance. In the linear region, with small VDS, as VGS increases, the inversion charge increases. Therefore, the capacitance value increases. In the saturation region, because of the pinch-off phenomenon, the inversion charge is solely due to the gate-source voltage and the capacitance value is maximum. This behavior is followed by the simulation results.

The variations of gate-to-drain capacitor CGD with VDS for three different values of VGS are shown in Figure 7.33. In the subthreshold region, the inversion charge is negligibly small so that CGD is ideally zero. In the saturation region, due to the pinch-off phenomenon, there is no capacitive coupling

analog and RF IC design. The two most important noise components of a MOS transistor are thermal noise and flicker noise. The following subsections deal with each of them individually.

7.8.1  Characterization of Thermal Noise in MOS Transistor

In conventional resistors, the thermal noise is generated due to the random thermal motion of the electrons. This motion does not depend upon the presence or absence of direct current, because the drift velocities of electrons in a conductor are much less than the thermal velocities of the electrons. In a resistor R, the thermal noise is represented by a series voltage generator or a shunt current generator to a noiseless ideal resistor. The noise spectral density is given by [3,5]

In (7.135) and (7.136), k represents Boltzmann’s constant. From (7.135) and (7.136), it is observed that the noise spectral density is independent of frequency f. This characteristic is called white noise.

The intrinsic thermal noise of a MOS transistor originates from the channel resistance due to random thermal motion of the carriers. The channel of a MOS transistor may be considered to be divided into several resistive segments, and each of these segments contributes to thermal noise. The corresponding noise spectral density thus follows (7.135). The resistor R is replaced by (2/3)gm, in a saturation region where gm is the gate transconductance of the device. It follows, therefore, from (7.135) that

However, (7.137) is inadequate, especially in the linear region VDS ≈ 0 where the transconductance is zero, so that the calculated noise spectral density becomes zero, which however is not true in practice. Thus (7.137) is modified as follows:

In (7.138), gds and gmb are output conductance and body transconductance, respectively. However, a more rigorous approach for characterizing thermal noise is given below which is widely used in SPICE compact models [3,6,7].