Книги+1 / 2013 [Chandan_Kumar_Sarkar]_Technology_CAD

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266Technology Computer Aided Design: Simulation for VLSI MOSFET

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7.9.2Sources of Random Intra-Die Process Variations and Their

7.1 Introduction

With the continual downscaling of metal-oxide-semiconductor (MOS) transistors to the sub-90 nm regime, several secondary issues related to the transistor device physics, hitherto considered to be insignificant, are found to play significant roles in circuit performances. The circuit designers therefore need proper understanding of the various parameters related to geometry as well as performances of a single MOS transistor and the effect of these on the performances of an overall very large scale integrated (VLSI) circuit. A detailed characterization of the MOS transistor device to be used by them for the design is therefore an essential requirement prior to the design task, especially in sub-90 nm design domain. The objective of this chapter is to present a comprehensive discussion on the characterization of sub-90 nm MOS transistor for VLSI circuit simulation purpose. The discussion is limited to conventional bulk MOS transistor only, because this has been the most widely used device for VLSI circuit simulation, considering the cost and expertise required for fabrication.

The pedagogical approach used in this chapter is that initially the various characteristics are discussed qualitatively. This is followed by introduction

of standard mathematical models. The use of these models in a BSIM4 compact model (which is one of the most widely used industry standard compact models) is thereafter discussed briefly. The purpose of this chapter is to present the primary important characteristics of VLSI metal-oxide-semiconductor field-effect transistor (MOSFET) to the integrated circuit (IC) designers in a manner such that they are aware of the internal workings of the SPICE simulation tool. The readers are encouraged to refer to appropriate BSIM manuals and SPICE model user guides for the exact mathematical formulations and the complete modeling works. SPICE simulation results are provided to support the theoretical discussion, as required.

The rest of the chapter is organized as follows. Section 7.2 emphasizes the importance of the use of device models for VLSI circuit simulation. The various categories of device models and the publicly available device models are also discussed. Section 7.3 presents the detailed characterization of the threshold voltage of an n-channel enhancement mode transistor. Section 7.4 discusses the I-V characteristics, supported with results. Sections 7.5 and 7.6 discuss the impact ionization process and the gate dielectric model. Characterizations of MOS capacitances are discussed in Section 7.7. Noise and statistical characterization are discussed in Sections 7.8 and 7.9, respectively. Finally, Section 7.10 presents a summary and conclusion of the chapter.

7.2  Device Models for Circuit Simulation

7.2.1  Necessity of Device Models

An outline of the IC simulation procedure is illustrated in Figure 7.1. The procedure starts with a set of desired specifications for the circuit to be designed. This acts as the input to the procedure. A particular topology of the circuit (transistor-level topology) is then selected by the designer. This choice is primarily based upon the designer’s experience. The circuit is described either schematically or through a textual description, referred to as the netlist of the circuit. The circuit is subsequently analyzed through SPICE simulation tool. The SPICE simulation tool internally uses a set of device models for the components of the circuits and solves a set of network theory equations through standard numerical algorithms [1].

The performance parameters of the circuit are extracted and compared with the desired specifications. If the extracted parameters satisfy the desired specifications, the design is completed. Otherwise the simulation procedure is carried out iteratively either by changing the circuit description or circuit parameters and conducting further analyses until the specifications are satisfied.

From 1970 onward, SPICE has been the sole tool used by IC designers for circuit simulation. The development of this tool started at the University

FIGURE 7.1

Outline of the IC simulation flow.

of California, Berkeley, in the late 1960s and continued until the 1990s. The commercial SPICE simulation tools used today by designers (e.g., HSPICE [Synopsys], SPECTRE [Cadence], ELDO [Mentor Graphics]) are all based upon the original SPICE simulation tool developed at the University of California. All of these simulators internally use appropriate device models for faithful description of behaviors of the devices used in the circuit. Thus the use of appropriate device models, not the internal algorithms, is responsible for the success of a circuit simulation program [2]. The accuracy and reliability of a circuit simulation process in predicting the device performances accurately depend upon the accuracy of the internal device models.

7.2.2  Definition and Categories of Device Models

Device models are defined as the link between the physical world (technology, manufacturing, etc.) and the design world (device simulation, timing

simulation, etc.) of the semiconductor industry [3]. There are three categories of device models: numerical models, look-up table models, and analytical or compact models. The numerical models are based upon numerical solutions of carrier transport equations, device geometry, and doping profile-related equations. Although these techniques provide accurate results, they are computationally very intensive. Therefore these techniques are not suitable for simulation of large circuits. However, these may be used for exploration of novel device structures and associated performances. The TCAD device simulation tools as discussed in the earlier chapters are based upon this approach. The look-up table approach, on the other hand, uses measured device current and capacitances (and in some cases small signal parameters) as functions of bias voltages and device sizes for characterizing device performances that are subsequently used for circuit simulation purposes. This approach is used when good physical models of any device are not available and is sometimes used in fast circuit simulators. The most popular approach that is used for circuit simulation purpose is the third approach (i.e., the use of analytical or compact models). A compact model is characterized by a set of mathematical equations whose parameters are used as inputs to a SPICE-like circuit simulation program [3]. The physical compact model equations are derived based upon the physics of the device. These equations are expected to reproduce the device characteristics for different device dimensions, range of temperature, process variations, etc. Good physical compact models are usually complex because they consider several physical phenomena. In order to make the equations simple so as to avoid the convergence problem of the circuit simulator, some approximations are sometimes judiciously made keeping the physics intact. Fitting parameters are often introduced to improve the accuracy of the model. Apart from accuracy, a desirable requirement from a compact model is some prediction capability. This helps the designers to predict any statistical behavior of the circuit and to explore circuit performances under migrated technology.

7.2.3  Commercially Used Compact Models

The development of a physical compact model for a MOS transistor began in the 1970s. Since then, more than 100 models, including MOS 1, MOS 2, MOS 3, MOS 9, PCIM, Level 28, ISIM, BSIM1 (Berkeley Short Channel IGFET Model), BSIM2 and BSIM 3, BSIM 4, PSP (Pennsylvania State University’s Surface Potential Model), HiSIM (Hiroshima University STARC IGFET Model), and EKV (Enz-Krummenacher-Vittoz) have been reported. Out of them, BSIM3, BSIM 4 PSP, HiSIM, and EKV are mostly used in commercial circuit simulators. The basic idea behind the development of all of these models is to include exact physics-based analytical equations in the model structure and then use fitting parameters to calibrate the equations with measured results. The generations of compact models have evolved to include more and more physical effects of the transistor device and thus to make the models more and more accurate.