13-16
CHUNG-YU WU
5.DE2 (The same as DE1), DV' : residual voltage
6.INT(ZI)
RINT |
CINT |
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C3 |
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100p |
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IN LO |
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The final residual voltage DV' is effectively reduced to 1 of the original 10
residual voltage without amplification.
Þ accuracy -
13-17
CHUNG-YU WU
§13-4 Algorithmic ADC
Refs: 1. IEEE ISSCC, Digest of Papers, pp. 96-97, 1977
* 2. IEEE JSSC, vol. 31, no. 8, pp. 1201-1207, Aug. 1996
Sample/Hold |
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Comparator |
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S/H |
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V(i) |
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Comp. |
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multiplier |
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B(i) |
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x2 |
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+ Vref |
Σ
- Vref
The conceptual block diagram of the algorithmic A/D converter
*The speed is limited by the settling time of OP AMPs used to implement the multiplier.
*For audio ADC applications, it could reach low-power low-voltage operation.
*Major error sources: (1) Capacitor ratio mismatches if SC circuits are used.
(2)Finite-gain error of OP amps.
(3)Offset voltage of OP amps.
(4)Capacitor feedthrough error by switches if SC circuits are used.
13-18
CHUNG-YU WU
Complete circuit of the ratio-independent and gain-insensitive algorithmic
ADCs |
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1+2 |
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1+2+3+4+5 |
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1+2+3+4 |
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2 |
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C3 |
S4 |
C4 |
5 |
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3+4+6+7 |
C7 |
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C2 |
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8*1 |
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(B) |
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S6 3+6 |
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S2 |
1 |
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S3 3+4+6+7 |
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8 |
1+2 |
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S1 |
5 |
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(C) |
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Vin |
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(A) |
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Vref |
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C1 |
OP1 |
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3+4+6+7 |
OP2 |
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+ |
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4 |
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S5 |
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4 |
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3+4+5+6+7 |
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C5 |
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C6 |
3+7 |
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3+4+7 |
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b8*1 |
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3+6 |
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7 |
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b8(1+2) |
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6+7+1 |
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2 |
C8 |
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S7 |
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Latch |
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(D) |
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7+1 |
comp. |
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Q |
bBit |
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Q |
Bit |
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switch |
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The complete circuit of the A/D converter
Clock waveforms:
1 |
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2 |
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3 |
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4 |
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5 |
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6 |
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7 |
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1 |
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8
- +
+ - 
bBit
13-23
CHUNG-YU WU
A typical plot of the differential nonlinearity.
A typical plot of the integral nonlinearity.
13-24
CHUNG-YU WU
A typical FFT plot of the A/D converter.
Table I The Experimental results of the proposed A/D converter.
Resolution |
14 bits |
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Differential nonlinearity |
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1/2 LSB |
Integral nonlinearity |
± |
1 LSB |
Sampling frequency |
10 KHz |
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Gain of op amp |
60 dB |
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Power dissipation |
50 mWatts |
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Supply voltage |
± 2.5 V |
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Process |
0.8 μm CMOS |
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Chip active area |
2.1mm × 0.8mm |
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