13-5
CHUNG-YU WU
§13-2 Successive-Approximation (SA) ADC's
§13-2.1 Resistor-string SA MOS ADC
Ref. : IEEE J. Solid-State Circuits, vol. Sc-13, pp. 785-791, Dec. 1978.
Conceptual 3-bit unipolar ADC
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VREF |
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3R |
C C |
B B A A |
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Comparator |
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Output |
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VIN |
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Typical performance of a 8-bit ADC: |
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p-type resistor |
Resolution |
8 bit |
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100Ω/ |
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Nonlinearity |
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1 LSB |
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DNL |
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1 LSB |
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10 |
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Conversion time |
20 μs |
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Input resistance |
>1000 MΩ |
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Stability (0o - 85oC) |
<1/4 LSB |
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Error Sources:
1.Resistor matching accuracy.
*Dividing the string into several equal lengths and locating them in close proximity.
13-6
CHUNG-YU WU
2.The reverse bias junction voltage of the diffused resistors causes nonlinearity. Bit capacity - Þ W/ 
¯ .
3.The small on resistance of the switches can decrease the settling time and reduce the feedthrough effect from the gate voltages. Similary, the switch feedthrough only effects the settling time.
4.Major error source: The feedthrough in the switch transistor Q2.
1MHz clock → 2 mV error.
5.Comparator offset error.
§13-2.2 Charge-Balancing SA MOS ADC
Ref. : IEEE J. Solid-State Circuits, pp. 912-920, Dec. 1979.
* Mixed resistor string and binary-weighed cap.
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Vref |
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3rd |
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MSB |
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data |
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2nd |
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LSB |
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MSB |
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C |
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R/4 |
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R/8 |
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T1 |
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C/16 |
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1/2 LSB |
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R/8 |
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Shift |
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T2 |
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C/16 |
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8-bit ADC |
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C=20pF |
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Linearity |
1/4LSB |
Supply Voltage |
4.5 - 6.3 V |
Conversion Time |
100 ms |
Current Drain |
1.8mA |
640 KHz clock |
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VREF Range |
0 - 5 V |
Analog Input |
0 - VDD |
Clock Freq. Range |
100 - 800 KHz |
Components used: |
8R's, 4C's, 32 switches. |
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13-7 |
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CHUNG-YU WU |
13-bit ADC with laser-cut programmable Si-Cr fuse PROM's. |
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Post-process triming |
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Linearity |
1/2 LSB |
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Conversion Time |
50 μs |
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Analog input |
Vss ~ Vcc |
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Clock freq. range |
0.1 ~ 3MHz |
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Supply voltage |
± 4.5 ~ ±6.3V |
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Current drain |
5mA |
§13-2.3 Charge-Redistribution SA MOS ADC (CRSA ADC)
1. 10-bit CRSA ADC
Ref: IEEE JSSC, vol. SC-10, pp. 371-379, 379-385, Dec.1975.
Operation Procedures
(a) Sample Mode:
(b) Hold Mode:
13-8
CHUNG-YU WU
(c) Redistribution (Approximation) Mode:
S1 → Vref , |
Vx = -Vin + Vref /2 |
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If Vx < 0, |
logic 1 in MSB(b4), |
Vin > Vref |
/2 |
If Vx > 0, |
b4(MSB)=0, |
Vin < Vref |
/2 and S1 → ground |
Final Configuration:
Vx = − Vin + Vref ( + b4 + b3 + b2 + b1 + b0 ) ≈ 0 21 22 23 2 4 25
Vx = − Vin + Vref (24 b4 + 23 b3 + 22 b2 +21 b1 + 20 b0 ), Vin > 0 25
13-9
CHUNG-YU WU
Complete ADC block diagram:
Measured Results: |
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Resolution |
10 bits |
Gain error |
0.05 % |
Linearity |
± 1 LSB |
Sample mode |
2.3μs |
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2 |
acquisition time |
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Input Voltage |
0-10 V |
Total conversion |
22.8 μs |
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time |
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Input offset |
2mV |
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13-10
CHUNG-YU WU
2. 12-bit modified CRSA ADC
Ref.: IEEE J. Solid-State Circuits, vol. sc-14, pp. 920-926, Dec. 1979.
VREF |
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R1 |
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R2 |
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SF |
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Ck |
C3 |
C2 |
C1 |
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k+1 |
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R3 |
2k-1C 2k-2C |
2C |
C C |
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Comparator |
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SA |
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2 -1 |
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CLOCK |
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SWITCH |
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SUCCESSIVE APPROX. REGISTER |
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CONTROL |
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+ SWITCH CONTROL LOGIC |
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VIN |
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(M+K) BIT OUTPUT OF A/D |
START |
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*SAMPLE
*HOLD
*CHOOSE Vref
VREF |
S5 |
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Voltage A- |
SA |
SB |
S1 |
S2 |
S3 |
S4 |
S5 |
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B |
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R1 |
S4 |
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Vref |
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R2 |
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S3 |
1 |
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1/2 VREF |
SA |
Smaller |
Vref |
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1 |
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R3 |
S2 |
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1/4 VREF |
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discharge |
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ON |
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0 |
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set-up |
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redistribution |
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13-12
CHUNG-YU WU
Set up |
1 |
2 |
OFF OFF OFF |
ON |
ON |
B |
… . |
B |
B |
OFF |
− Vin + |
3Vref |
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(Vref) (3Vref/4) |
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Redistribution |
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-Vin+(3/4)Vref < Vx < -Vin + Vref |
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OFF OFF OFF |
ON |
ON |
A |
… . |
B |
B |
OFF |
− Vin + |
3Vref |
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+ 18 Vref
* The last capacitor C is always connected to B.
13-13
CHUNG-YU WU
§13-3 Dual-Slope ( Integrating; Charge-Balancing ) MOS ADC's
4 1 Digit ADC (Modified structure)
2
LATCH, DECODER, |
DISPLAY MULTIPLEXER |
UP/DOWN RESULTS COUNTER |
SEQUENCE COUNTER |
/ DECODER |
CONTROL |
LOGIC |
ANALOG |
SECTION |
CREF
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REF HI |
REF LO |
RINT |
CINT |
X10 |
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DE |
DE |
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C2 |
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COMPARATOR 1 |
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<10> |
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INT1 |
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COMPARATOR 2 |
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A |
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DE- |
DE+ |
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BUFFER |
INTEGRATOR C3 |
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<100> |
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DE+ |
DE- |
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COMMON |
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ZI , X10 |
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TO DIGITAL |
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INT |
REST |
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IN LO |
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INT1,IN2,INT |
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13-14
CHUNG-YU WU
Waveforms observed at the node A :
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V ' |
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INT1 |
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DE1 |
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RESET |
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X10 |
DE2 |
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INT(ZI) |
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INT2 |
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NOTE: ENCLOSED AREA GREATLY EXPENDED IN TIME AND AMPLITUDE
Operational principles: 1. INT1
REF HI REF LO
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CREF |
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RINT |
CINT |
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- + |
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- |
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Comparator 1 |
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IN HI |
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Comparator 2 |
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COMMON |
+ |
C3 |
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100p |
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IN LO |
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