Micro-Cap v7.1.6 / RM
.PDF
Parameter |
Description |
Units |
Default |
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AtoD3 |
AtoD interface circuit for level 3 |
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AtoDDefault |
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DtoA3 |
DtoA interface circuit for level 3 |
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DtoADefault |
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AtoD4 |
AtoD interface circuit for level 4 |
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AtoDDefault |
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DtoA4 |
DtoA interface circuit for level 4 |
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DtoADefault |
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TSWLH1 |
Low to high switching time for DtoA1 |
sec |
0 |
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TSWLH2 |
Low to high switching time for DtoA2 |
sec |
0 |
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TSWLH3 |
Low to high switching time for DtoA3 |
sec |
0 |
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TSWLH4 |
Low to high switching time for DtoA4 |
sec |
0 |
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TSWHL1 |
High to low switching time for DtoA1 |
sec |
0 |
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TSWHL2 |
High to low switching time for DtoA2 |
sec |
0 |
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TSWHL3 |
High to low switching time for DtoA3 |
sec |
0 |
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TSWHL4 |
High to low switching time for DtoA4 |
sec |
0 |
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TPWRT |
Pulse width rejection threshold |
sec |
prop delay |
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DIGPOWER |
Power supply subcircuit name |
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DIGIFPWR |
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Table 23-22 I/O model parameters (continued)
INLD and OUTLD are used to compute the optional loading delay. This value increases the propagation delay through the device to account for excessive capacitive loading on the node caused by high fan-out. Fan-out is the number of gate inputs connected to a device's output.
DRVH and DRVL are the high state and low state impedances used to determine output strength. Strength is used to resolve the output state when a digital output is connected to other digital outputs.
DRVZ, INR, and TSTOREMN are used to determine which nodes are to be treated as charge storage nets. Charge storage nets are not available in the current version.
AtoD1 through AtoD4 and DtoA1 through DtoA4 supply the names of the interface circuits. INLD and the AtoD names do not apply to stimulus sources since
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Digital / analog interface devices
When a digital node and an analog node are connected together in a circuit, the system breaks the connections and inserts between the two parts the interface circuit specified in the I/O model. These interface circuits contain analog devices like resistors, capacitors, diodes, and transistors. They also contain either an analog to digital or digital to analog interface device. These devices provide the fundamental translation between the analog and digital circuits.
Digital input device (N device)
When a digital output node is connected to an analog node, the interface circuit requires an N device. Its function is to translate digital levels to analog voltages and impedances to drive the analog node.
SPICE format
N<name> <interface node> <low level node> <high level node> +<model name>
+ DGTLNET=<digital node name> +<I/O model name>
+[IS=<initial state>]
Schematic format
PART attribute <name>
Example
FS1
MODEL attribute <model name>
Example
D0_AD
I/O MODEL attribute <I/O model name>
Example
IO_STD
590 Chapter 23: Digital Devices
IS attribute <initial state>
Example 1
Model form
.MODEL <model name> DINPUT ([model parameters])
Parameter |
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Description |
Units |
Default |
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CLO |
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Capacitance to low level node |
farad |
0 |
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CHI |
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Capacitance to high level node |
farad |
0 |
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S0NAME |
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State '0' character abbreviation |
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S0TSW |
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State '0' switching time |
sec |
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S0RLO |
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State '0' resistance to low level node |
ohm |
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S0RHI |
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State '0' resistance to high level node |
ohm |
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S1NAME |
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State '1' character abbreviation |
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S1TSW |
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State '1' switching time |
sec |
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S1RLO |
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State '1' resistance to low level node |
ohm |
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S1RHI |
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State '1' resistance to high level node |
ohm |
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. |
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. |
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. |
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. |
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. |
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. |
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S19NAME |
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State '19' resistance to high level node |
ohm |
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S19TSW |
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State '19' switching time |
sec |
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S19RLO |
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State '19' resistance to low level node |
ohm |
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S19RHI |
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State '19' resistance to high level node |
ohm |
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Table 23-23 The N device model parameters |
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591 |
When a digital device output is connected to an analog node, MC7 automatically breaks the connection and inserts the DtoA circuit specified in the I/O model. That circuit always employs an N device, whose function is to translate the digital states to impedance changes on the analog side. The process is described in more detail in the "The analog / digital interface" section in this chapter.
The equivalent circuit of the N device is as follows:
Figure 23-8 N device equivalent circuit
The N device contains two resistors and two optional capacitors. The resistance of the resistors changes in response to changes in the digital input. In a SPICE file, the digital input node is specified by <digital node name>. In a schematic, the digital input node is simply the node associated with the 'Digital' pin of the N device. When this digital input node changes from a '0' to a '1', the value of RHI changes linearly versus time from the '0' state high resistance to the '1' state high resistance. Similarly, the value of RLO changes linearly versus time from the '0' state low resistance to the '1' state low resistance.
The transition from the old resistance to the new resistance is accomplished in a linear fashion over the switching time specified in the DINPUT model for the new state. The output voltage changes from the old level to the new level during the switching time. The output curve looks somewhat like an exponential due to the simultaneous change of the two resistor values. The transition values of resistance for each state are obtained from the DINPUT model. Normally the <high level node> and <low level node> are connected to the voltage sources that correspond to the highest and lowest logic levels. The connection is usually made within the particular DtoA interface circuit called for in the I/O model.
592 Chapter 23: Digital Devices
Digital output device (O device)
When a digital input node is connected to an analog node, the A/D interface circuit requires an O device. Its function is to translate analog voltages into digital levels on the digital node.
SPICE format
O<name> <interface node> <reference node> +<model name>
+ DGTLNET=<digital node name> +<I/O model name>
Schematic format
PART attribute <name>
Example
FS1
MODEL attribute <model name>
Example
D_AD
I/O MODEL attribute <I/O model name>
Example
IO_STD
When a digital device input is connected to an analog node, the system automatically breaks the connection and inserts the AtoD circuit specified in the I/O model. That circuit always employs an O device. The function of the O device is to translate the analog voltages on the analog side to digital states on the digital side. The exact process is described in more detail in the "The analog/digital Interface" section of this chapter.
Model form
.MODEL <model name> DOUTPUT ([model parameters])
594 Chapter 23: Digital Devices
