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material1 / different / Chung-Yu Wu - Analog Circuit Design

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11-13

CHUNG-YU WU

Conventional Weighted-Current-Source D/A Converter

YU-CHUNG

13-11

WU

 

11-14

CHUNG-YU WU

Improved Structure

The Proposed 10-bit D/A Converter

Reference: IEEE JSSC, PP.635-639, June 1989.

1. Using Two-Stage Architecture:

32 master & 32 slave current sources

(Occupied small chip area but cause tight matching requirement

among master current sources.)

2. Using Threshold-Voltage Compensated Current Sources

to satisify tight matching requirement.

Only need local match &

do not need global match.

YU-CHUNG

14-11

WU

 

11-15

CHUNG-YU WU

Two-Stage Weighted Current Array D/A Converter

YU-CHUNG

15-11

WU

 

11-16

CHUNG-YU WU

I1 = K (W/L)(Va-Vth1)2

IN = K (W/L)(Va-VthN)2

(VthN-Vth1) may be as large as 80 mV due to the oxide thinning effect.

Conventional switched current source.

YU-CHUNG

16-11

WU

 

11-17

CHUNG-YU WU

I

2

= K W

(Va -Vth

2

)2

 

 

 

 

L

 

 

 

 

 

 

 

 

 

= K W

(V

+Vth

c

-Vth

2

+

LcIc )2

 

 

L

R1

 

 

 

 

KWc

1.I2 IC

2.M2 and MC are locally matched

 

ÞI

@ K W V

VR1

2

L

R1

Switched current source with threshold-voltage compensation.

YU-CHUNG

17-11

WU

 

11-18

CHUNG-YU WU

Spice Monte-Carlo simulation results for (a) Conventional weighted current sources; (b) current sources with threshold-voltage compensation.

11-19

CHUNG-YU WU

To Coax

Y YB

D10

Driver

D6

 

A

 

 

 

 

Vdd

 

VB

VR2

 

 

 

 

Va

 

IMSB

 

 

 

VR1

 

Gnd

x16

 

 

 

 

Y

YB

 

 

 

D5

Driver

 

A

D1

 

 

 

 

 

 

 

 

 

 

 

Y

YB

 

 

 

 

Vdd

 

 

 

 

 

 

 

 

 

 

 

VR2

 

 

 

 

 

 

Vb

 

 

 

 

IMSB-5

 

 

 

 

 

 

 

x16

VR3

Driver

 

 

 

 

 

A

 

 

 

 

 

 

 

 

 

 

 

 

 

Vdd

 

 

 

Vdd

VB

 

VR2

 

 

VR2

 

 

 

 

 

c

 

Va

 

c

Va

IMSB-1

 

 

 

IMSB-4

 

 

 

x1

VR1

 

x1

VR1

 

 

 

 

 

Y

YB

To Dummy Load

 

 

Driver

A

Vdd

 

 

Vdd

Vdd

VR2

VR2

Vb

Vb

ILSB

I

 

LSB

VR3

VR3

x1

x1

Two-stage weighted-current-source D/A converter with threshold-voltage compensated current sources.

YU-CHUNG

19-11

WU

 

11-20

CHUNG-YU WU

CKs

Din

D

VB1

DB

VB1

Vdd

out

out

in VB1

in

 

VB1

 

Vss

(a)

(b)

(a) The circuit; (b) The SPICE simulated output waveforms of the input driver with high logic-threshold.

11-21

CHUNG-YU WU

16I

8I

4I

2I

I

I

Symmetrical layout configuration of each 5-bit current array.

Compact

Symmetry

 

 

 

 

 

M2

 

M2

M2 M2

Mc

M2 Mc

M2

M2

Different layout arrangement for the devices M2 and Mc in each current source: (a) 4-cell unit; (b) 5-cell unit.

11-22

CHUNG-YU WU

Differential linearity error of the D/A converter

Integral linearity error of the D/A converter.

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