11-3
CHUNG-YU WU
(4) Accuracy
absolute accuracy: The difference between the expected and actual transfer response. It includes the offset, gain, and linearity errors.
relative accuracy: The accuracy after the offset and gain errors have been removed.
Þ maximum integrated nonlinearity (INL) error *Accuracy units: % of full-scale value.
effective number of bits
fraction of an LSB
*12-bit accuracy Þ all errors 1 LSB ( Vout )
212
(5) Integral nonlinearity (INL) error
Definition: The deviation of actual transfer response from a straight line.
INL error (best-fit) and INL error (endpoint)
Usually, INL error is referred to as the maximum INL error.
Vout |
Best-fit |
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straight line |
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VLSB |
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Transfer response |
(maximum) INL error |
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without gain and |
(best-fit) |
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offset errors |
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Endpoint straight line
(maximum) INL error (endpoint)
11-4
CHUNG-YU WU
(6) Differential nonlinearity (DNL) error
Definition: The variation in analog step sizes away from 1 LSB. ( usually, gain and offset errors have been removed)
(7) Monotonicity: The output signal magnitude always increases as the input digital code increases.
* Maximum DNL error 0.5 LSBÞ monotonicity
*Many monotonic DAC may have a maximum DNL error 0.5 LSB
*Maximum INL error 0.5 LSBÞ monotonicity
(8)Settling time
The time it takes for the DAC to settle to within some specified amount of the final value (usually 0.5 LSB)
(9) Sampling rate
The rate at which sample can be continuously converted.
(Typically the sampling rate is equal to the inverse of the settling time)
4.Types of DACs
(1)Decoder-based DAC
(2)Binary-weighted DAC
(3)Thermometer-code DAC
(4)Hybrid DAC
(5)Oversampling DAC
11-5
CHUNG-YU WU
§11-2 Decoder-Based DAC
§11-2.1 Resistor-String DAC
1. Conceptual 8-bit resistor-string DAC.
REF+
S256
R
S255
R |
S254 |
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S253 |
DAC OUT |
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S3 |
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256 OUTPUTS |
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S2 |
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8 To 256 |
S1 |
DECODER |
REF- 
0 1 2 3 4 5 6 7
(DAC INPUTS)
2. Practical realization
R0-R15: To divide VREF+ to VREF- into 16 voltage intervals
H0-H15
L0-L15: To divide each of those intervals into 16
a - p subintervals
*To insure maximum uniformity of step size, i.e. linearity, the resistance of the transmission gates should be made as large as possible Þ minimal loading.
*For 8-bit DAC, the error due to loading can be held to less than 1 LSB.
if 16R |
2NR |
( R = 200 Ω , R 3.2KΩ ) |
T |
i |
i |
T |
11-6
CHUNG-YU WU
8-bit Resistor-String DAC (Multiple Resistor-String DAC)
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L0 |
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L1 |
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0 |
L2 |
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L3 |
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L4 |
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1 |
L5 |
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L6 |
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4:16 |
L7 |
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L8 |
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2 |
L9 |
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L10 |
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3 |
L11 |
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L12 |
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L13 |
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L14 |
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L15 |
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H0 |
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H1 |
0 |
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H2 |
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H3 |
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H4 |
1 |
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H5 |
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H6 |
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4:16 |
H7 |
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H8 |
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2 |
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H9 |
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H10 |
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H11 |
3 |
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H12 |
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H13 |
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H14 |
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H15 |
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R15 |
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H14 |
n14 |
H15 p15 |
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R14 |
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H13 |
n13 |
H14 p14 |
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R13 |
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H12 |
n12 |
H13 p13 |
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R12 |
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H11 |
n11 |
H12 p12 |
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R11 |
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H10 |
n10 |
H11 p11 |
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R10 |
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H9 |
n9 |
H10 p10 |
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R9 |
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H8 |
n8 |
H9 |
p9 |
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R8 |
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H7 |
n7 |
H8 |
p8 |
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R7 |
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H6 |
n6 |
H7 |
p7 |
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R6 |
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H5 |
n5 |
H6 |
p6 |
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R5 |
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H4 |
n4 |
H5 |
p5 |
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R4 |
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H3 |
n3 |
H4 |
p4 |
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R3 |
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H2 |
n2 |
H3 |
p3 |
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R2 |
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H1 |
n1 |
H2 |
p2 |
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R1 |
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H0 |
n0 |
H1 |
p1 |
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R0 |
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H0 |
p0 |
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REF- |
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L15 |
o |
L0 |
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L14 |
n |
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L13 |
m |
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L12 |
l |
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L11 |
k |
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L10 |
j |
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L9 |
i |
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DAC OUT |
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L8 |
h |
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L7 |
g |
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L6 |
f |
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L5 |
e |
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L4 |
d |
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L3 |
c |
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L2 |
b |
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L0+L1 |
a |
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Subinterval Generation:
14R T's
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Lo |
L15 |
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Transmission- |
L14 |
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gate resistor |
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L13 |
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L12 |
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L11 |
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L10 |
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L9 |
RT |
Hi |
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L8 |
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L7 |
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Ri+1 |
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Ri |
RT |
L6 |
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200 Ω
L5
Ri-1 
Hi
L4
L3
RT=3.2KΩ
L2
L0+L1
*Transmission gate size: 24μ /12μ ®3.2kW=RT
*The raw speed of the DAC is limited by the resistance of transmission gates a-p and the capacitance of the output node, also by the operating speed of the output buffer.
*VDD = +5V, -VSS = -5V, Vout : ±2.5V
Maximum conversion rate 0 → full scale : 2.5MHz.
* For 8-bit DAC, the jump in step size can be held to less than 1 LSB if
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R i |
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16RT Ri |
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16R ³ |
N |
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DR i |
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Ri +16RT |
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R i |
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2 R . |
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R i |
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Ri +16RT |
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2N |
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Þ 2N R |
£16R |
T |
occurs when L =1 |
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11-8
CHUNG-YU WU
§11-2.2 Folded Multiple Resistor-String DAC
11-11
CHUNG-YU WU
§11-3 Binary-Weighted DAC
§11-3.1 Charge-Redistribution DAC
1.Multiplying DAC
*All top plates are connected to the OP AMP input
ÞTo reduce substrate noise voltage injection.
*Switched-induced errors are large.
*offset cancellation
2.Multiplying DAC with bipolar input
LSB
MSB
sign bit
If bo = 0 Þ the signal Vin is positive Þ the same as 1.
11-12
CHUNG-YU WU
If b0 = 1 |
Þ the signal Vin is negative. |
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φ1, φ2 positions are exchanged. |
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n |
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Vout = -Vin åbi2−i |
i=1
3.General characteristics or features of charge-redistribution DAC:
(1)The auto-calibration cycle can be performed to remove the effects of component ratio errors.
(2)Good linearity and stability due to good linear capacitors.
(3)Too large capacitance ratio is required for high-bit DAC.
(4)Suitable for medium-speed DAC with 6-bit resolution or below.
§11-3.2 Weighted-Current-Source DAC (Current-Mode Binary-
Weighted DAC)
Conceptual circuit:
1.Conventional structure
*Simple circuit structure without decoding logic.
*At the mid-code transition 011---1→ 10---0, the MSB current source needs to be matched to the sum of all the other current sources to within 0.5 LSB.
Þdifficult for large bit number.
Þnot guaranteed monotonic.
*Low-accuracy matching causes inaccurate bit transition
Þ typical DNL plot as shown →
* The errors caused by the dynamic behavior of the switches, such as charge injection and clock feedthrough, result in glitches which is most severe at the midcode transition, as all switches are switching simultaneously.
Þcontains highly nonlinear signal components
Þmanifest itself as spurs in the frequency domain.
maximum
Midcode glitches
Transfer
response
Reference: IEEE Journal of Solid-State Circuits, vol.33, pp.1948-1958, Dec.1998.
