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PIC18F2455/2550/4455/4550

16.4.2PWM DUTY CYCLE

The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits. Up to 10-bit resolution is available. The CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The PWM duty cycle is calculated by the following equation.

EQUATION 16-2:

PWM Duty Cycle = (CCPR1L:CCP1CON<5:4> • TOSC • (TMR2 Prescale Value)

CCPR1L and CCP1CON<5:4> can be written to at any time, but the duty cycle value is not copied into CCPR1H until a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPR1H is a read-only register.

The CCPR1H register and a 2-bit internal latch are used to double-buffer the PWM duty cycle. This double-buffering is essential for glitchless PWM operation. When the CCPR1H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or two bits of the TMR2 prescaler, the CCP1 pin is cleared. The maximum PWM resolution (bits) for a given PWM frequency is given by the following equation.

EQUATION 16-3:

 

log(

FOSC

)

 

PWM Resolution (max) =

FPWM

bits

 

 

 

 

log(2)

 

 

 

 

 

Note: If the PWM duty cycle value is longer than the PWM period, the CCP1 pin will not be cleared.

16.4.3PWM OUTPUT CONFIGURATIONS

The P1M1:P1M0 bits in the CCP1CON register allow one of four configurations:

Single Output

Half-Bridge Output

Full-Bridge Output, Forward mode

Full-Bridge Output, Reverse mode

The Single Output mode is the standard PWM mode discussed in Section 16.4 “Enhanced PWM Mode”. The Half-Bridge and Full-Bridge Output modes are covered in detail in the sections that follow.

The general relationship of the outputs in all configurations is summarized in Figure 16-2 and Figure 16-3.

TABLE 16-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz

PWM Frequency

2.44 kHz

9.77 kHz

39.06 kHz

156.25 kHz

312.50 kHz

416.67 kHz

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Timer Prescaler (1, 4, 16)

16

4

1

1

1

1

 

 

 

 

 

 

 

PR2 Value

FFh

FFh

FFh

3Fh

1Fh

17h

 

 

 

 

 

 

 

Maximum Resolution (bits)

10

10

10

8

7

6.58

 

 

 

 

 

 

 

DS39632D-page 152

Preliminary

2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

FIGURE 16-2: PWM OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE)

 

 

0

Duty

PR2 + 1

 

CCP1CON

SIGNAL

 

 

Cycle

 

 

<7:6>

 

 

 

 

 

Period

 

 

 

 

00

(Single Output)

P1A Modulated

 

 

 

 

Delay(1)

 

Delay(1)

 

 

P1A Modulated

 

 

10

(Half-Bridge)

P1B Modulated

 

 

 

 

P1A Active

 

 

01

(Full-Bridge,

P1B Inactive

 

 

Forward)

 

 

 

 

 

P1C Inactive

 

 

 

 

P1D Modulated

 

 

 

 

P1A Inactive

 

 

11

(Full-Bridge,

P1B Modulated

 

 

Reverse)

 

 

 

 

P1C Active

 

 

 

 

 

 

 

 

P1D Inactive

 

 

FIGURE 16-3: PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE)

 

CCP1CON

SIGNAL

0

Duty

PR2 + 1

 

 

 

 

 

Cycle

 

 

<7:6>

 

 

 

 

 

 

 

Period

 

 

 

 

 

00

(Single Output)

P1A Modulated

 

 

 

 

 

P1A Modulated

 

 

Delay(1)

10

(Half-Bridge)

P1B Modulated

 

Delay(1)

 

 

 

 

 

P1A Active

 

 

 

01

(Full-Bridge,

P1B Inactive

 

 

 

Forward)

 

 

 

 

 

 

P1C Inactive

 

 

 

 

 

P1D Modulated

 

 

 

 

 

P1A Inactive

 

 

 

11

(Full-Bridge,

P1B Modulated

 

 

 

 

 

 

 

Reverse)

 

 

 

 

 

P1C Active

 

 

 

 

 

 

 

 

 

 

P1D Inactive

 

 

 

Relationships:

 

 

 

 

• Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)

 

 

 

• Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value)

 

• Delay = 4 * TOSC * (ECCP1DEL<6:0>)

 

 

 

Note 1:

Dead-band delay is programmed using the ECCP1DEL register (Section 16.4.6 “Programmable Dead-Band Delay”).

2007 Microchip Technology Inc.

Preliminary

DS39632D-page 153

PIC18F2455/2550/4455/4550

16.4.4HALF-BRIDGE MODE

In the Half-Bridge Output mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the P1A pin, while the complementary PWM output signal is output on the P1B pin (Figure 16-4). This mode can be used for half-bridge applications, as shown in Figure 16-5, or for full-bridge applications where four power switches are being modulated with two PWM signals.

In Half-Bridge Output mode, the programmable dead-band delay can be used to prevent shoot-through current in half-bridge power devices. The value of bits PDC6:PDC0 sets the number of instruction cycles before the output is driven active. If the value is greater than the duty cycle, the corresponding output remains inactive during the entire cycle. See Section 16.4.6 “Programmable Dead-Band Delay” for more details of the dead-band delay operations.

Since the P1A and P1B outputs are multiplexed with the PORTC<2> and PORTD<5> data latches, the TRISC<2> and TRISD<5> bits must be cleared to configure P1A and P1B as outputs.

FIGURE 16-4: HALF-BRIDGE PWM OUTPUT

Period

 

Period

Duty Cycle

P1A(2)

td

td P1B(2)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(1)

 

(1)

 

(1)

 

 

 

 

 

 

 

 

 

 

 

 

td = Dead-Band Delay

Note 1: At this time, the TMR2 register is equal to the PR2 register.

2: Output signals are shown as active-high.

FIGURE 16-5: EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS

V+

Standard Half-Bridge Circuit (“Push-Pull”)

PIC18FX455/X550

FET

 

 

Driver

+

 

 

P1A

 

V

 

 

-

 

FET

Load

 

 

 

Driver

+

 

 

P1B

 

V

 

 

-

V-

Half-Bridge Output Driving a Full-Bridge Circuit

 

V+

 

PIC18FX455/X550

 

 

FET

 

FET

Driver

 

Driver

P1A

 

 

FET

Load

FET

 

Driver

 

Driver

P1B

 

 

 

V-

 

DS39632D-page 154

Preliminary

2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

16.4.5FULL-BRIDGE MODE

In Full-Bridge Output mode, four pins are used as outputs; however, only two outputs are active at a time. In the Forward mode, pin P1A is continuously active and pin P1D is modulated. In the Reverse mode, pin P1C is continuously active and pin P1B is modulated. These are illustrated in Figure 16-6.

P1A, P1B, P1C and P1D outputs are multiplexed with the PORTC<2>, PORTD<5>, PORTD<6> and PORTD<7> data latches. The TRISC<2>, TRISD<5>, TRISD<6> and TRISD<7> bits must be cleared to make the P1A, P1B, P1C and P1D pins outputs.

FIGURE 16-6: FULL-BRIDGE PWM OUTPUT

Forward Mode

Period

P1A(2)

Duty Cycle

P1B(2)

P1C(2)

P1D(2)

(1)

 

 

 

 

 

(1)

 

 

 

 

 

 

 

 

Reverse Mode

Period

Duty Cycle

P1A(2)

P1B(2)

P1C(2)

P1D(2)

(1)

 

 

 

(1)

 

Note 1: At this time, the TMR2 register is equal to the PR2 register.

2: Output signal is shown as active-high.

2007 Microchip Technology Inc.

Preliminary

DS39632D-page 155

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