19.4.2OPERATION

The MSSP module functions are enabled by setting MSSP Enable bit, SSPEN (SSPCON1<5>).

The SSPCON1 register allows control of the I2C operation. Four mode selection bits (SSPCON1<3:0>) allow one of the following I2C modes to be selected:

•I2C Master mode, clock

•I2C Slave mode (7-bit address)

•I2C Slave mode (10-bit address)

•I2C Slave mode (7-bit address) with Start and Stop bit interrupts enabled

•I2C Slave mode (10-bit address) with Start and Stop bit interrupts enabled

•I2C Firmware Controlled Master mode, slave is Idle

Selection of any I2C mode with the SSPEN bit set forces the SCL and SDA pins to be open-drain, provided these pins are programmed as inputs by setting the appropriate TRISC or TRISD bits. To ensure proper operation of the module, pull-up resistors must be provided externally to the SCL and SDA pins.

19.4.3SLAVE MODE

In Slave mode, the SCL and SDA pins must be configured as inputs (TRISC<4:3> set). The MSSP module will override the input state with the output data when required (slave-transmitter).

The I2C Slave mode hardware will always generate an interrupt on an address match. Address masking will allow the hardware to generate an interrupt for more than one address (up to 31 in 7-bit addressing and up to 63 in 10-bit addressing). Through the mode select bits, the user can also choose to interrupt on Start and Stop bits.

When an address is matched, or the data transfer after an address match is received, the hardware automatically will generate the Acknowledge (ACK) pulse and load the SSPBUF register with the received value currently in the SSPSR register.

Any combination of the following conditions will cause the MSSP module not to give this ACK pulse:

•The Buffer Full bit, BF (SSPSTAT<0>), was set before the transfer was received.

•The overflow bit, SSPOV (SSPCON1<6>), was set before the transfer was received.

In this case, the SSPSR register value is not loaded into the SSPBUF, but bit SSPIF is set. The BF bit is cleared by reading the SSPBUF register, while bit SSPOV is cleared through software.

The SCL clock input must have a minimum high and low for proper operation. The high and low times of the I2C specification, as well as the requirement of the MSSP module, are shown in timing parameter 100 and parameter 101.

19.4.3.1Addressing

Once the MSSP module has been enabled, it waits for a Start condition to occur. Following the Start condition, the 8 bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock (SCL) line. The value of register SSPSR<7:1> is compared to the value of the SSPADD register. The address is compared on the falling edge of the eighth clock (SCL) pulse. If the addresses match and the BF and SSPOV bits are clear, the following events occur:

1.The SSPSR register value is loaded into the SSPBUF register.

2.The Buffer Full bit, BF, is set.

3.An ACK pulse is generated.

4.The MSSP Interrupt Flag bit, SSPIF, is set (and interrupt is generated, if enabled) on the falling edge of the ninth SCL pulse.

In 10-Bit Address mode, two address bytes need to be received by the slave. The five Most Significant bits (MSbs) of the first address byte specify if this is a 10-bit address. Bit R/W (SSPSTAT<2>) must specify a write so the slave device will receive the second address byte. For a 10-bit address, the first byte would equal ‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the two MSbs of the address. The sequence of events for 10-bit address is as follows, with steps 7 through 9 for the slave-transmitter:

1.Receive first (high) byte of address (bits SSPIF, BF and UA (SSPSTAT<1>) are set on address match).

2.Update the SSPADD register with second (low) byte of address (clears bit UA and releases the SCL line).

3.Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF.

4.Receive second (low) byte of address (bits SSPIF, BF and UA are set).

5.Update the SSPADD register with the first (high) byte of address. If match releases SCL line, this will clear bit UA.

6.Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF.

7.Receive Repeated Start condition.

8.Receive first (high) byte of address (bits SSPIF and BF are set).

9.Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF.

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19.4.3.2Address Masking

Masking an address bit causes that bit to become a “don’t care”. When one address bit is masked, two addresses will be Acknowledged and cause an interrupt. It is possible to mask more than one address bit at a time, which makes it possible to Acknowledge up to 31 addresses in 7-bit mode and up to 63 addresses in 10-bit mode (see Example 19-2).

The I2C Slave behaves the same way whether address masking is used or not. However, when address masking is used, the I2C slave can Acknowledge multiple addresses and cause interrupts. When this occurs, it is necessary to determine which address caused the interrupt by checking SSPBUF.

In 7-Bit Address mode, address mask bits ADMSK<5:1> (SSPCON2<5:1>) mask the corresponding address bits in the SSPADD register. For any ADMSK bits that are set (ADMSK<n> = 1), the corresponding address bit is ignored (SSPADD<n> = x). For the module to issue an address Acknowledge, it is sufficient to match only on addresses that do not have an active address mask.

In 10-Bit Address mode, bits ADMSK<5:2> mask the corresponding address bits in the SSPADD register. In addition, ADMSK1 simultaneously masks the two LSbs of the address (SSPADD<1:0>). For any ADMSK bits that are active (ADMSK<n> = 1), the corresponding address bit is ignored (SSPADD<n> = x). Also note that although in 10-Bit Addressing mode, the upper address bits reuse part of the SSPADD register bits, the address mask bits do not interact with those bits. They only affect the lower address bits.

Note 1: ADMSK1 masks the two Least Significant bits of the address.

2:The two Most Significant bits of the address are not affected by address masking.

19.4.3.3Reception

When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register and the SDA line is held low (ACK).

When the address byte overflow condition exists, then the no Acknowledge (ACK) pulse is given. An overflow condition is defined as either bit BF (SSPSTAT<0>) is set, or bit SSPOV (SSPCON1<6>) is set.

An MSSP interrupt is generated for each data transfer byte. The Interrupt Flag bit, SSPIF, must be cleared in software. The SSPSTAT register is used to determine the status of the byte.

If SEN is enabled (SSPCON2<0> = 1), RB1/AN10/ INT1/SCK/SCL will be held low (clock stretch) following each data transfer. The clock must be released by setting bit, CKP (SSPCON1<4>). See Section 19.4.4 “Clock Stretching” for more detail.

19.4.3.4Transmission

When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set. The received address is loaded into the SSPBUF register. The ACK pulse will be sent on the ninth bit and pin RB1/AN10/INT1/SCK/ SCL is held low regardless of SEN (see Section 19.4.4 “Clock Stretching” for more detail). By stretching the clock, the master will be unable to assert another clock pulse until the slave is done preparing the transmit data. The transmit data must be loaded into the SSPBUF register which also loads the SSPSR register. Then pin RB1/AN10/INT1/SCK/SCL should be enabled by setting bit, CKP (SSPCON1<4>). The eight data bits are shifted out on the falling edge of the SCL input. This ensures that the SDA signal is valid during the SCL high time (Figure 19-10).

The ACK pulse from the master-receiver is latched on the rising edge of the ninth SCL input pulse. If the SDA line is high (not ACK), then the data transfer is complete. In this case, when the ACK is latched by the slave, the slave logic is reset (resets SSPSTAT register) and the slave monitors for another occurrence of the Start bit. If the SDA line was low (ACK), the next transmit data must be loaded into the SSPBUF register. Again, pin RB1/AN10/INT1/SCK/SCL must be enabled by setting bit CKP (SSPCON1<4>).

An MSSP interrupt is generated for each data transfer byte. The SSPIF bit must be cleared in software and the SSPSTAT register is used to determine the status of the byte. The SSPIF bit is set on the falling edge of the ninth clock pulse.

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SSPIF (PIR1<3>)

Bus master terminates transfer

BF (SSPSTAT<0>)

Cleared in software

SSPBUF is read

SSPOV (SSPCON1<6>)

SSPOV is set because SSPBUF is

still full. ACK is not sent.

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Preliminary

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SSPIF (PIR1<3>)

Bus master terminates transfer

BF (SSPSTAT<0>)

Cleared in software

SSPBUF is read

SSPOV (SSPCON1<6>)

SSPOV is set because SSPBUF is

still full. ACK is not sent.

CKP

(CKP does not reset to ‘0’ when SEN = 0)

Note 1: x = Don’t care (i.e., address bit can be either a ‘1’ or a ‘0’).

2:In this example, an address equal to A7.A6.A5.X.A3.X.X will be Acknowledged and cause an interrupt.

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P

Cleared in software

From SSPIF ISR

SSPBUF is written in software

CKP is set in software

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