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PIC18F2455/2550/4455/4550

26.2.2EXTENDED INSTRUCTION SET

ADDFSR

 

 

Add Literal to FSR

 

 

Syntax:

 

 

ADDFSR

 

f, k

 

 

Operands:

 

 

0 ≤ k ≤ 63

 

 

 

 

 

 

f [ 0, 1, 2 ]

 

 

Operation:

 

 

FSR(f) + k → FSR(f)

 

 

Status Affected:

 

 

None

 

 

 

 

 

 

Encoding:

 

 

1110

1000

ffkk

 

kkkk

 

 

 

 

 

 

 

 

 

 

Description:

 

 

The 6-bit literal ‘k’ is added to the

 

 

 

 

contents of the FSR specified by ‘f’.

Words:

 

1

 

 

 

 

 

 

Cycles:

 

1

 

 

 

 

 

 

Q Cycle Activity:

 

 

 

 

 

 

 

 

 

 

Q1

 

 

Q2

 

Q3

 

Q4

 

Decode

 

 

Read

 

Process

 

Write to

 

 

 

literal ‘k’

 

Data

 

 

FSR

Example:

 

ADDFSR

2, 23h

 

 

 

Before Instruction

 

 

 

 

 

 

 

FSR2

=

 

03FFh

 

 

 

 

 

 

 

After Instruction

 

 

 

 

 

 

 

 

 

FSR2

=

 

0422h

 

 

 

 

 

 

ADDULNK

 

Add Literal to FSR2 and Return

Syntax:

 

ADDULNK k

 

 

 

 

Operands:

 

0 ≤ k ≤ 63

 

 

 

 

 

 

Operation:

 

FSR2 + k → FSR2,

 

 

 

 

 

 

 

(TOS) → PC

 

 

 

 

Status Affected:

 

None

 

 

 

 

 

 

Encoding:

 

1110

 

1000

 

11kk

 

kkkk

 

 

 

 

 

 

 

 

 

Description:

 

The 6-bit literal ‘k’ is added to the

 

 

 

contents of FSR2. A RETURN is then

 

 

 

executed by loading the PC with the

 

 

 

TOS.

 

 

 

 

 

 

 

 

 

The instruction takes two cycles to

 

 

 

execute; a NOP is performed during

 

 

 

the second cycle.

 

 

 

 

 

 

 

This may be thought of as a special

 

 

 

case of the ADDFSR instruction,

 

 

 

where f = 3 (binary ‘11’); it operates

 

 

 

only on FSR2.

 

 

 

 

Words:

1

 

 

 

 

 

 

 

Cycles:

2

 

 

 

 

 

 

 

Q Cycle Activity:

 

 

 

 

 

 

 

 

 

 

Q1

 

Q2

Q3

 

 

 

Q4

 

Decode

 

Read

Process

 

Write to

 

 

literal ‘k’

Data

 

 

 

FSR

 

No

 

No

No

 

 

 

No

 

Operation

Operation

Operation

 

Operation

Example:

ADDULNK 23h

 

 

 

 

Before Instruction

FSR2 = 03FFh

PC = 0100h

After Instruction

FSR2 = 0422h

PC = (TOS)

Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction syntax then becomes: {label} instruction argument(s).

DS39632D-page 350

Preliminary

2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

CALLW

 

Subroutine Call Using WREG

 

 

 

 

 

 

 

 

 

 

Syntax:

 

CALLW

 

 

 

 

 

 

Operands:

 

None

 

 

 

 

 

 

Operation:

 

(PC + 2) → TOS,

 

 

 

 

 

(W) → PCL,

 

 

 

 

 

(PCLATH) → PCH,

 

 

 

 

 

(PCLATU) → PCU

 

 

Status Affected:

 

None

 

 

 

 

 

 

Encoding:

 

 

 

 

 

 

 

 

 

0000

0000

0001

 

0100

 

 

 

 

 

 

 

 

 

Description

 

First, the return address (PC + 2) is

 

 

 

pushed onto the return stack. Next, the

 

 

 

contents of W are written to PCL; the

 

 

 

existing value is discarded. Then the

 

 

 

contents of PCLATH and PCLATU are

 

 

 

latched into PCH and PCU,

 

 

 

 

 

respectively. The second cycle is

 

 

 

executed as a NOP instruction while the

 

 

 

new next instruction is fetched.

 

 

 

Unlike CALL, there is no option to

 

 

 

update W, STATUS or BSR.

Words:

 

1

 

 

 

 

 

 

Cycles:

 

2

 

 

 

 

 

 

Q Cycle Activity:

 

 

 

 

 

 

 

 

 

Q1

 

Q2

 

Q3

 

Q4

 

Decode

 

Read

 

Push PC to

 

 

No

 

 

 

WREG

 

stack

 

operation

 

No

 

No

 

No

 

 

No

 

operation

operation

 

operation

 

operation

Example:

 

HERE

 

CALLW

 

 

 

Before Instruction

 

 

 

 

 

 

 

PC

=

address (HERE)

 

 

 

PCLATH =

10h

 

 

 

 

 

 

 

PCLATU =

00h

 

 

 

 

 

 

 

W

=

06h

 

 

 

 

 

 

 

After Instruction

 

 

 

 

 

 

 

 

PC

=

001006h

 

 

 

TOS

=

address (HERE + 2)

 

 

 

PCLATH =

10h

 

 

 

 

 

 

 

PCLATU =

00h

 

 

 

 

 

 

 

W

=

06h

 

 

 

 

 

 

MOVSF

 

Move Indexed to f

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Syntax:

 

MOVSF

[zs], fd

 

 

 

 

 

Operands:

 

0 ≤ zs ≤ 127

 

 

 

 

 

 

 

 

0 ≤ fd ≤ 4095

 

 

 

 

 

Operation:

 

((FSR2) + zs) → fd

 

 

 

 

 

Status Affected:

 

None

 

 

 

 

 

 

 

 

 

Encoding:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1st word (source)

 

1110

 

1011

 

0zzz

 

zzzzs

2nd word (destin.)

 

1111

 

 

ffff

 

ffff

 

ffffd

Description:

 

The contents of the source register are

 

 

 

moved to destination register ‘fd’. The

 

 

 

actual address of the source register is

 

 

 

determined by adding the 7-bit literal

 

 

 

offset ‘zs’ in the first word to the value of

 

 

 

FSR2. The address of the destination

 

 

 

register is specified by the 12-bit literal

 

 

 

‘fd’ in the second word. Both addresses

 

 

 

can be anywhere in the 4096-byte data

 

 

 

space (000h to FFFh).

 

 

 

 

 

 

The MOVSF instruction cannot use the

 

 

 

PCL, TOSU, TOSH or TOSL as the

 

 

 

destination register.

 

 

 

 

 

 

 

 

If the resultant source address points to

 

 

 

an indirect addressing register, the

 

 

 

value returned will be 00h.

 

 

 

Words:

2

 

 

 

 

 

 

 

 

 

Cycles:

2

 

 

 

 

 

 

 

 

 

Q Cycle Activity:

 

 

 

 

 

 

 

 

 

 

 

 

Q1

 

Q2

 

 

Q3

 

 

 

 

Q4

 

Decode

Determine

 

Determine

 

 

Read

 

 

source addr

 

source addr

 

source reg

 

Decode

 

No

 

 

No

 

 

 

Write

 

 

operation

 

operation

 

register ‘f’

 

 

No dummy

 

 

 

 

 

 

(dest)

 

 

 

read

 

 

 

 

 

 

 

 

 

Example:

 

MOVSF

 

[05h], REG2

 

 

 

 

Before Instruction

 

 

 

 

 

 

 

 

 

 

FSR2

=

80h

 

 

 

 

 

 

Contents

 

 

 

 

 

 

 

 

 

 

 

 

of 85h

=

33h

 

 

 

 

 

 

REG2

=

11h

 

 

 

 

 

 

After Instruction

 

 

 

 

 

 

 

 

 

 

FSR2

=

80h

 

 

 

 

 

 

Contents

 

 

 

 

 

 

 

 

 

 

 

 

of 85h

=

33h

 

 

 

 

 

 

REG2

=

33h

 

 

 

 

 

2007 Microchip Technology Inc.

Preliminary

DS39632D-page 351

PIC18F2455/2550/4455/4550

MOVSS

 

Move Indexed to Indexed

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Syntax:

 

MOVSS

[zs], [zd]

 

 

 

 

 

Operands:

 

0 ≤ zs

≤ 127

 

 

 

 

 

 

 

 

 

 

0 ≤ zd

≤ 127

 

 

 

 

 

 

 

Operation:

 

((FSR2) + zs) → ((FSR2) + zd)

Status Affected:

 

None

 

 

 

 

 

 

 

 

 

 

 

Encoding:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1st word (source)

 

1110

 

 

 

1011

 

1zzz

 

zzzzs

2nd word (dest.)

 

1111

 

 

 

xxxx

 

xzzz

 

zzzzd

Description

 

The contents of the source register are

 

 

 

moved to the destination register. The

 

 

 

addresses of the source and destination

 

 

 

registers are determined by adding the

 

 

 

7-bit literal offsets ‘zs’ or ‘zd’,

 

 

 

 

 

respectively, to the value of FSR2. Both

 

 

 

registers can be located anywhere in

 

 

 

the 4096-byte data memory space

 

 

 

(000h to FFFh).

 

 

 

 

 

 

 

 

The MOVSS instruction cannot use the

 

 

 

PCL, TOSU, TOSH or TOSL as the

 

 

 

destination register.

 

 

 

 

 

 

 

 

If the resultant source address points to

 

 

 

an indirect addressing register, the

 

 

 

value returned will be 00h. If the

 

 

 

resultant destination address points to

 

 

 

an indirect addressing register, the

 

 

 

instruction will execute as a NOP.

Words:

2

 

 

 

 

 

 

 

 

 

 

 

Cycles:

2

 

 

 

 

 

 

 

 

 

 

 

Q Cycle Activity:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Q1

 

Q2

 

 

 

 

Q3

 

 

 

 

Q4

 

Decode

Determine

 

Determine

 

 

Read

 

 

source addr

 

source addr

 

source reg

 

Decode

Determine

 

Determine

 

 

Write

 

 

dest addr

 

dest addr

 

to dest reg

Example:

 

MOVSS

[05h], [06h]

 

 

 

 

Before Instruction

 

 

 

 

 

 

 

 

 

 

 

 

FSR2

=

 

80h

 

 

 

 

 

 

Contents

 

 

 

 

 

 

 

 

 

 

 

 

 

 

of 85h

=

 

33h

 

 

 

 

 

 

Contents

 

 

 

 

 

 

 

 

 

 

 

 

 

 

of 86h

=

 

11h

 

 

 

 

 

 

After Instruction

 

 

 

 

 

 

 

 

 

 

 

 

FSR2

=

 

80h

 

 

 

 

 

 

Contents

 

 

 

 

 

 

 

 

 

 

 

 

 

 

of 85h

=

 

33h

 

 

 

 

 

 

Contents

 

 

 

 

 

 

 

 

 

 

 

 

 

 

of 86h

=

 

33h

 

 

 

 

 

PUSHL

Store Literal at FSR2, Decrement FSR2

 

 

 

 

 

 

 

 

 

 

 

Syntax:

PUSHL k

 

 

 

 

 

 

 

Operands:

0 ≤ k ≤ 255

 

 

 

 

 

 

 

Operation:

k → (FSR2),

 

 

 

 

 

 

 

 

 

FSR2 – 1→ FSR2

 

 

 

 

 

Status Affected:

None

 

 

 

 

 

 

 

Encoding:

 

 

 

 

 

 

 

 

 

 

1111

 

1010

 

kkkk

 

kkkk

 

 

 

 

 

 

 

 

 

Description:

The 8-bit literal ‘k’ is written to the data

 

 

memory address specified by FSR2. FSR2

 

 

is decremented by ‘1’ after the operation.

 

 

This instruction allows users to push values

 

 

onto a software stack.

 

 

Words:

1

 

 

 

 

 

 

 

 

 

Cycles:

1

 

 

 

 

 

 

 

 

 

Q Cycle Activity:

 

 

 

 

 

 

 

 

 

 

 

Q1

 

Q2

 

 

Q3

 

Q4

 

Decode

 

Read ‘k’

 

Process

 

Write to

 

 

 

 

 

 

 

data

 

destination

Example:

 

PUSHL

08h

 

 

 

 

 

 

Before Instruction

 

 

 

 

 

 

 

 

FSR2H:FSR2L

=

 

01ECh

 

 

 

Memory (01ECh)

=

 

00h

 

 

 

After Instruction

 

 

 

 

 

 

 

 

FSR2H:FSR2L

=

 

01EBh

 

 

 

Memory (01ECh)

=

 

08h

 

 

DS39632D-page 352

Preliminary

2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

SUBFSR

 

Subtract Literal from FSR

 

Syntax:

 

SUBFSR f, k

 

 

 

Operands:

 

0 ≤ k ≤ 63

 

 

 

 

 

 

 

 

 

f [ 0, 1, 2 ]

 

 

 

Operation:

 

FSRf – k → FSRf

 

 

 

Status Affected:

 

None

 

 

 

 

 

 

Encoding:

 

1110

 

1001

ffkk

 

kkkk

 

 

 

 

 

 

 

 

 

 

 

Description:

 

The 6-bit literal ‘k’ is subtracted from

 

 

 

 

the contents of the FSR specified by

 

 

 

 

‘f’.

 

 

 

 

 

 

Words:

 

1

 

 

 

 

 

 

 

Cycles:

 

1

 

 

 

 

 

 

 

Q Cycle Activity:

 

 

 

 

 

 

 

 

 

 

Q1

 

Q2

Q3

 

Q4

 

 

Decode

 

Read

Process

 

Write to

 

 

 

register ‘f’

Data

 

destination

 

Example:

 

SUBFSR 2, 23h

 

 

 

 

Before Instruction

 

 

 

 

 

 

 

 

 

FSR2

=

03FFh

 

 

 

 

 

 

 

After Instruction

 

 

 

 

 

 

 

 

 

FSR2

=

03DCh

 

 

 

 

 

 

SUBULNK

Subtract Literal from FSR2 and Return

Syntax:

SUBULNK k

 

 

 

 

 

 

Operands:

0 ≤ k ≤ 63

 

 

 

 

 

 

Operation:

FSR2 – k → FSR2

 

 

 

 

 

 

 

(TOS) → PC

 

 

 

 

 

 

Status Affected:

None

 

 

 

 

 

 

 

 

Encoding:

1110

 

1001

 

11kk

 

kkkk

 

 

 

 

 

 

 

 

 

Description:

The 6-bit literal ‘k’ is subtracted from the

 

 

contents of the FSR2. A RETURN is then

 

 

executed by loading the PC with the TOS.

 

 

The instruction takes two cycles to

 

 

execute; a NOP is performed during the

 

 

second cycle.

 

 

 

 

 

 

 

 

This may be thought of as a special case of

 

 

the SUBFSR instruction, where f = 3 (binary

 

 

11’); it operates only on FSR2.

 

 

Words:

1

 

 

 

 

 

 

 

 

 

Cycles:

2

 

 

 

 

 

 

 

 

 

Q Cycle Activity:

 

 

 

 

 

 

 

 

 

Q1

 

 

Q2

 

Q3

 

Q4

 

Decode

 

Read

 

Process

 

Write to

 

 

 

register ‘f’

 

Data

 

destination

 

No

 

 

No

 

No

 

 

No

 

Operation

 

Operation

Operation

 

Operation

Example:

 

SUBULNK 23h

 

 

 

Before Instruction

 

 

 

 

 

 

 

 

 

FSR2

=

03FFh

 

 

 

 

 

 

 

PC

=

0100h

 

 

 

 

 

 

 

After Instruction

 

 

 

 

 

 

 

 

 

FSR2

=

03DCh

 

 

 

 

 

 

 

PC

=

(TOS)

 

 

 

 

 

 

2007 Microchip Technology Inc.

Preliminary

DS39632D-page 353

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