PIC18F2455/2550/4455/4550
4.6Reset State of Registers
Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a “Reset state” depending on the type of Reset that occurred.
Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal oper- ation. Status bits from the RCON register, RI, TO, PD, POR and BOR, are set or cleared differently in different Reset situations as indicated in Table 4-3. These bits are used in software to determine the nature of the Reset.
Table 4-4 describes the Reset states for all of the Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets and WDT wake-ups.
TABLE 4-3: |
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION |
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FOR RCON REGISTER |
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Condition |
Program |
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RCON Register |
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STKPTR Register |
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Counter |
SBOREN |
RI |
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TO |
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PD |
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POR |
BOR |
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STKFUL |
STKUNF |
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Power-on Reset |
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0000h |
1 |
1 |
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1 |
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1 |
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0 |
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0 |
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0 |
0 |
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RESET Instruction |
0000h |
u(2) |
0 |
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u |
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u |
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u |
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u |
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u |
u |
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Brown-out |
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0000h |
u(2) |
1 |
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1 |
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1 |
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u |
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0 |
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u |
u |
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during Power-Managed |
0000h |
u(2) |
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MCLR |
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u |
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1 |
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u |
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u |
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u |
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u |
u |
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Run modes |
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during Power-Managed |
0000h |
u(2) |
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MCLR |
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u |
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1 |
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0 |
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u |
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u |
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u |
u |
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Idle modes and Sleep mode |
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WDT Time-out during Full Power |
0000h |
u(2) |
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u |
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0 |
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u |
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u |
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u |
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u |
u |
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or Power-Managed Run modes |
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during Full Power |
0000h |
u(2) |
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MCLR |
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u |
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u |
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u |
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u |
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u |
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u |
u |
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Execution |
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Stack Full Reset (STVREN = 1) |
0000h |
u(2) |
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u |
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u |
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u |
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u |
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u |
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1 |
u |
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Stack Underflow Reset |
0000h |
u(2) |
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u |
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u |
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u |
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u |
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u |
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u |
1 |
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(STVREN = 1) |
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Stack Underflow Error (not an |
0000h |
u(2) |
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u |
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u |
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u |
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u |
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u |
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u |
1 |
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actual Reset, STVREN = 0) |
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WDT Time-out during |
PC + 2 |
u(2) |
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u |
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0 |
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0 |
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u |
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u |
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u |
u |
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Power-Managed Idle or Sleep |
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modes |
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Interrupt Exit from |
PC + 2(1) |
u(2) |
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u |
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u |
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0 |
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u |
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u |
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u |
u |
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Power-Managed modes |
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Legend: u = unchanged |
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Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (008h or 0018h).
2:Reset state is ‘1’ for POR and unchanged for all other Resets when software BOR is enabled (BOREN1:BOREN0 Configuration bits = 01 and SBOREN = 1); otherwise, the Reset state is ‘0’.
DS39632D-page 50 |
Preliminary |
♥ 2007 Microchip Technology Inc. |
PIC18F2455/2550/4455/4550
TABLE 4-4: |
INITIALIZATION CONDITIONS FOR ALL REGISTERS |
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MCLR Resets, |
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Register |
Applicable Devices |
Power-on Reset, |
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WDT Reset, |
Wake-up via WDT |
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Brown-out Reset |
RESET Instruction, |
or Interrupt |
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Stack Resets |
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TOSU |
2455 |
2550 |
4455 |
4550 |
---0 0000 |
---0 0000 |
---0 uuuu(1) |
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TOSH |
2455 |
2550 |
4455 |
4550 |
0000 0000 |
0000 0000 |
uuuu uuuu(1) |
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TOSL |
2455 |
2550 |
4455 |
4550 |
0000 0000 |
0000 0000 |
uuuu uuuu(1) |
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STKPTR |
2455 |
2550 |
4455 |
4550 |
00-0 0000 |
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uu-0 0000 |
uu-u uuuu(1) |
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PCLATU |
2455 |
2550 |
4455 |
4550 |
---0 0000 |
---0 0000 |
---u uuuu |
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PCLATH |
2455 |
2550 |
4455 |
4550 |
0000 0000 |
0000 0000 |
uuuu uuuu |
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PCL |
2455 |
2550 |
4455 |
4550 |
0000 0000 |
0000 0000 |
PC + 2(3) |
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TBLPTRU |
2455 |
2550 |
4455 |
4550 |
--00 0000 |
--00 0000 |
--uu uuuu |
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TBLPTRH |
2455 |
2550 |
4455 |
4550 |
0000 0000 |
0000 0000 |
uuuu uuuu |
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TBLPTRL |
2455 |
2550 |
4455 |
4550 |
0000 0000 |
0000 0000 |
uuuu uuuu |
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TABLAT |
2455 |
2550 |
4455 |
4550 |
0000 0000 |
0000 0000 |
uuuu uuuu |
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PRODH |
2455 |
2550 |
4455 |
4550 |
xxxx xxxx |
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uuuu uuuu |
uuuu uuuu |
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PRODL |
2455 |
2550 |
4455 |
4550 |
xxxx xxxx |
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uuuu uuuu |
uuuu uuuu |
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INTCON |
2455 |
2550 |
4455 |
4550 |
0000 |
000x |
0000 |
000u |
uuuu uuuu(2) |
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INTCON2 |
2455 |
2550 |
4455 |
4550 |
1111 |
-1-1 |
1111 |
-1-1 |
uuuu -u-u(2) |
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INTCON3 |
2455 |
2550 |
4455 |
4550 |
11-0 0-00 |
11-0 0-00 |
uu-u u-uu(2) |
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INDF0 |
2455 |
2550 |
4455 |
4550 |
N/A |
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N/A |
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POSTINC0 |
2455 |
2550 |
4455 |
4550 |
N/A |
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N/A |
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POSTDEC0 |
2455 |
2550 |
4455 |
4550 |
N/A |
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N/A |
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PREINC0 |
2455 |
2550 |
4455 |
4550 |
N/A |
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N/A |
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PLUSW0 |
2455 |
2550 |
4455 |
4550 |
N/A |
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N/A |
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FSR0H |
2455 |
2550 |
4455 |
4550 |
---- 0000 |
---- 0000 |
---- uuuu |
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FSR0L |
2455 |
2550 |
4455 |
4550 |
xxxx xxxx |
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uuuu uuuu |
uuuu uuuu |
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WREG |
2455 |
2550 |
4455 |
4550 |
xxxx xxxx |
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uuuu uuuu |
uuuu uuuu |
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INDF1 |
2455 |
2550 |
4455 |
4550 |
N/A |
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N/A |
N/A |
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POSTINC1 |
2455 |
2550 |
4455 |
4550 |
N/A |
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N/A |
N/A |
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POSTDEC1 |
2455 |
2550 |
4455 |
4550 |
N/A |
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N/A |
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PREINC1 |
2455 |
2550 |
4455 |
4550 |
N/A |
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N/A |
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PLUSW1 |
2455 |
2550 |
4455 |
4550 |
N/A |
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N/A |
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FSR1H |
2455 |
2550 |
4455 |
4550 |
---- 0000 |
---- 0000 |
---- uuuu |
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FSR1L |
2455 |
2550 |
4455 |
4550 |
xxxx xxxx |
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uuuu uuuu |
uuuu uuuu |
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BSR |
2455 |
2550 |
4455 |
4550 |
---- 0000 |
---- 0000 |
---- uuuu |
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Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
2:One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
3:When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h).
4:See Table 4-3 for Reset value for specific condition.
5:PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’.
♥ 2007 Microchip Technology Inc.
Preliminary
DS39632D-page 51
PIC18F2455/2550/4455/4550
TABLE 4-4: |
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) |
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MCLR Resets, |
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Register |
Applicable Devices |
Power-on Reset, |
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WDT Reset, |
Wake-up via WDT |
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Brown-out Reset |
RESET Instruction, |
or Interrupt |
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Stack Resets |
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INDF2 |
2455 |
2550 |
4455 |
4550 |
N/A |
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N/A |
N/A |
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POSTINC2 |
2455 |
2550 |
4455 |
4550 |
N/A |
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N/A |
N/A |
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POSTDEC2 |
2455 |
2550 |
4455 |
4550 |
N/A |
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N/A |
N/A |
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PREINC2 |
2455 |
2550 |
4455 |
4550 |
N/A |
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N/A |
N/A |
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PLUSW2 |
2455 |
2550 |
4455 |
4550 |
N/A |
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N/A |
N/A |
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FSR2H |
2455 |
2550 |
4455 |
4550 |
---- 0000 |
---- 0000 |
---- uuuu |
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FSR2L |
2455 |
2550 |
4455 |
4550 |
xxxx xxxx |
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uuuu uuuu |
uuuu uuuu |
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STATUS |
2455 |
2550 |
4455 |
4550 |
---x xxxx |
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---u uuuu |
---u uuuu |
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TMR0H |
2455 |
2550 |
4455 |
4550 |
0000 0000 |
0000 0000 |
uuuu uuuu |
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TMR0L |
2455 |
2550 |
4455 |
4550 |
xxxx xxxx |
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uuuu uuuu |
uuuu uuuu |
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T0CON |
2455 |
2550 |
4455 |
4550 |
1111 1111 |
1111 1111 |
uuuu uuuu |
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OSCCON |
2455 |
2550 |
4455 |
4550 |
0100 q000 |
0100 |
00q0 |
uuuu uuqu |
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HLVDCON |
2455 |
2550 |
4455 |
4550 |
0-00 0101 |
0-00 0101 |
u-uu uuuu |
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WDTCON |
2455 |
2550 |
4455 |
4550 |
---- ---0 |
---- ---0 |
---- ---u |
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RCON(4) |
2455 |
2550 |
4455 |
4550 |
0q-1 11q0 |
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0q-q qquu |
uq-u qquu |
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TMR1H |
2455 |
2550 |
4455 |
4550 |
xxxx xxxx |
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uuuu uuuu |
uuuu uuuu |
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TMR1L |
2455 |
2550 |
4455 |
4550 |
xxxx xxxx |
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uuuu uuuu |
uuuu uuuu |
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T1CON |
2455 |
2550 |
4455 |
4550 |
0000 0000 |
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u0uu uuuu |
uuuu uuuu |
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TMR2 |
2455 |
2550 |
4455 |
4550 |
0000 0000 |
0000 0000 |
uuuu uuuu |
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PR2 |
2455 |
2550 |
4455 |
4550 |
1111 1111 |
1111 1111 |
1111 1111 |
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T2CON |
2455 |
2550 |
4455 |
4550 |
-000 0000 |
-000 0000 |
-uuu uuuu |
||||
|
|
|
|
|
|
|
|
|
|||
SSPBUF |
2455 |
2550 |
4455 |
4550 |
xxxx xxxx |
|
uuuu uuuu |
uuuu uuuu |
|||
|
|
|
|
|
|
|
|
||||
SSPADD |
2455 |
2550 |
4455 |
4550 |
0000 0000 |
0000 0000 |
uuuu uuuu |
||||
|
|
|
|
|
|
|
|
||||
SSPSTAT |
2455 |
2550 |
4455 |
4550 |
0000 0000 |
0000 0000 |
uuuu uuuu |
||||
|
|
|
|
|
|
|
|
||||
SSPCON1 |
2455 |
2550 |
4455 |
4550 |
0000 0000 |
0000 0000 |
uuuu uuuu |
||||
|
|
|
|
|
|
|
|
||||
SSPCON2 |
2455 |
2550 |
4455 |
4550 |
0000 0000 |
0000 0000 |
uuuu uuuu |
||||
|
|
|
|
|
|
|
|
|
|||
ADRESH |
2455 |
2550 |
4455 |
4550 |
xxxx xxxx |
|
uuuu uuuu |
uuuu uuuu |
|||
|
|
|
|
|
|
|
|
|
|||
ADRESL |
2455 |
2550 |
4455 |
4550 |
xxxx xxxx |
|
uuuu uuuu |
uuuu uuuu |
|||
|
|
|
|
|
|
|
|
||||
ADCON0 |
2455 |
2550 |
4455 |
4550 |
--00 0000 |
--00 0000 |
--uu uuuu |
||||
|
|
|
|
|
|
|
|
|
|||
ADCON1 |
2455 |
2550 |
4455 |
4550 |
--00 0qqq |
|
--00 0qqq |
--uu uuuu |
|||
|
|
|
|
|
|
|
|
||||
ADCON2 |
2455 |
2550 |
4455 |
4550 |
0-00 0000 |
0-00 0000 |
u-uu uuuu |
||||
|
|
|
|
|
|
|
|
|
|
|
|
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
2:One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
3:When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h).
4:See Table 4-3 for Reset value for specific condition.
5:PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’.
DS39632D-page 52 |
Preliminary |
♥ 2007 Microchip Technology Inc. |
PIC18F2455/2550/4455/4550
TABLE 4-4: |
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) |
|||||||||
|
|
|
|
|
|
|
MCLR Resets, |
|
||
Register |
Applicable Devices |
Power-on Reset, |
|
WDT Reset, |
Wake-up via WDT |
|||||
Brown-out Reset |
RESET Instruction, |
or Interrupt |
||||||||
|
|
|
|
|
||||||
|
|
|
|
|
|
|
Stack Resets |
|
||
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
CCPR1H |
2455 |
2550 |
4455 |
4550 |
xxxx xxxx |
|
uuuu uuuu |
uuuu uuuu |
||
|
|
|
|
|
|
|
|
|
||
CCPR1L |
2455 |
2550 |
4455 |
4550 |
xxxx xxxx |
|
uuuu uuuu |
uuuu uuuu |
||
|
|
|
|
|
|
|
|
|
|
|
CCP1CON |
2455 |
2550 |
4455 |
4550 |
--00 0000 |
--00 0000 |
--uu uuuu |
|||
|
2455 |
2550 |
4455 |
4550 |
0000 0000 |
0000 0000 |
uuuu uuuu |
|||
CCPR2H |
2455 |
2550 |
4455 |
4550 |
xxxx xxxx |
|
uuuu uuuu |
uuuu uuuu |
||
|
|
|
|
|
|
|
|
|
||
CCPR2L |
2455 |
2550 |
4455 |
4550 |
xxxx xxxx |
|
uuuu uuuu |
uuuu uuuu |
||
|
|
|
|
|
|
|
|
|||
CCP2CON |
2455 |
2550 |
4455 |
4550 |
0000 0000 |
0000 0000 |
uuuu uuuu |
|||
|
|
|
|
|
|
|
|
|||
BAUDCON |
2455 |
2550 |
4455 |
4550 |
0100 0-00 |
0100 0-00 |
uuuu u-uu |
|||
|
|
|
|
|
|
|
|
|||
ECCP1DEL |
2455 |
2550 |
4455 |
4550 |
0000 0000 |
0000 0000 |
uuuu uuuu |
|||
|
|
|
|
|
|
|
|
|||
ECCP1AS |
2455 |
2550 |
4455 |
4550 |
0000 0000 |
0000 0000 |
uuuu uuuu |
|||
|
|
|
|
|
|
|
|
|||
CVRCON |
2455 |
2550 |
4455 |
4550 |
0000 0000 |
0000 0000 |
uuuu uuuu |
|||
|
|
|
|
|
|
|
|
|||
CMCON |
2455 |
2550 |
4455 |
4550 |
0000 0111 |
0000 0111 |
uuuu uuuu |
|||
|
|
|
|
|
|
|
|
|
||
TMR3H |
2455 |
2550 |
4455 |
4550 |
xxxx xxxx |
|
uuuu uuuu |
uuuu uuuu |
||
|
|
|
|
|
|
|
|
|
||
TMR3L |
2455 |
2550 |
4455 |
4550 |
xxxx xxxx |
|
uuuu uuuu |
uuuu uuuu |
||
|
|
|
|
|
|
|
|
|
||
T3CON |
2455 |
2550 |
4455 |
4550 |
0000 0000 |
|
uuuu uuuu |
uuuu uuuu |
||
|
|
|
|
|
|
|
|
|||
SPBRGH |
2455 |
2550 |
4455 |
4550 |
0000 0000 |
0000 0000 |
uuuu uuuu |
|||
|
|
|
|
|
|
|
|
|||
SPBRG |
2455 |
2550 |
4455 |
4550 |
0000 0000 |
0000 0000 |
uuuu uuuu |
|||
|
|
|
|
|
|
|
|
|||
RCREG |
2455 |
2550 |
4455 |
4550 |
0000 0000 |
0000 0000 |
uuuu uuuu |
|||
|
|
|
|
|
|
|
|
|||
TXREG |
2455 |
2550 |
4455 |
4550 |
0000 0000 |
0000 0000 |
uuuu uuuu |
|||
|
|
|
|
|
|
|
|
|||
TXSTA |
2455 |
2550 |
4455 |
4550 |
0000 0010 |
0000 0010 |
uuuu uuuu |
|||
|
|
|
|
|
|
|
|
|
||
RCSTA |
2455 |
2550 |
4455 |
4550 |
0000 000x |
|
0000 000x |
uuuu uuuu |
||
|
|
|
|
|
|
|
|
|||
EEADR |
2455 |
2550 |
4455 |
4550 |
0000 0000 |
0000 0000 |
uuuu uuuu |
|||
|
|
|
|
|
|
|
|
|||
EEDATA |
2455 |
2550 |
4455 |
4550 |
0000 0000 |
0000 0000 |
uuuu uuuu |
|||
|
|
|
|
|
|
|
|
|||
EECON2 |
2455 |
2550 |
4455 |
4550 |
0000 0000 |
0000 0000 |
0000 0000 |
|||
|
|
|
|
|
|
|
|
|
||
EECON1 |
2455 |
2550 |
4455 |
4550 |
xx-0 x000 |
|
uu-0 u000 |
uu-0 u000 |
||
|
|
|
|
|
|
|
|
|
|
|
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
2:One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
3:When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h).
4:See Table 4-3 for Reset value for specific condition.
5:PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’.
♥ 2007 Microchip Technology Inc.
Preliminary
DS39632D-page 53
PIC18F2455/2550/4455/4550
TABLE 4-4: |
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) |
||||||||||
|
|
|
|
|
|
|
|
MCLR Resets, |
|
||
Register |
Applicable Devices |
Power-on Reset, |
|
WDT Reset, |
Wake-up via WDT |
||||||
Brown-out Reset |
RESET Instruction, |
or Interrupt |
|||||||||
|
|
|
|
|
|||||||
|
|
|
|
|
|
|
|
Stack Resets |
|
||
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
IPR2 |
2455 |
2550 |
4455 |
4550 |
1111 |
1111 |
1111 |
1111 |
uuuu uuuu |
||
|
|
|
|
|
|
|
|
|
|
||
PIR2 |
2455 |
2550 |
4455 |
4550 |
0000 |
0000 |
0000 |
0000 |
uuuu uuuu(2) |
||
PIE2 |
2455 |
2550 |
4455 |
4550 |
0000 |
0000 |
0000 |
0000 |
uuuu uuuu |
||
|
|
|
|
|
|
|
|
|
|
|
|
IPR1 |
2455 |
2550 |
4455 |
4550 |
1111 |
1111 |
1111 |
1111 |
uuuu uuuu |
||
|
2455 |
2550 |
4455 |
4550 |
-111 1111 |
-111 1111 |
-uuu uuuu |
||||
PIR1 |
2455 |
2550 |
4455 |
4550 |
0000 |
0000 |
0000 |
0000 |
uuuu uuuu(2) |
||
|
2455 |
2550 |
4455 |
4550 |
-000 0000 |
-000 0000 |
-uuu uuuu |
||||
PIE1 |
2455 |
2550 |
4455 |
4550 |
0000 |
0000 |
0000 |
0000 |
uuuu uuuu |
||
|
2455 |
2550 |
4455 |
4550 |
-000 0000 |
-000 0000 |
-uuu uuuu |
||||
OSCTUNE |
2455 |
2550 |
4455 |
4550 |
0--0 0000 |
0--0 0000 |
u--u uuuu |
||||
|
|
|
|
|
|
|
|
|
|||
TRISE |
2455 |
2550 |
4455 |
4550 |
---- -111 |
---- -111 |
---- -uuu |
||||
TRISD |
2455 |
2550 |
4455 |
4550 |
1111 |
1111 |
1111 |
1111 |
uuuu uuuu |
||
TRISC |
2455 |
2550 |
4455 |
4550 |
11-- -111 |
11-- -111 |
uu-- -uuu |
||||
|
|
|
|
|
|
|
|
||||
TRISB |
2455 |
2550 |
4455 |
4550 |
1111 1111 |
1111 1111 |
uuuu uuuu |
||||
|
|
|
|
|
|
|
|
||||
TRISA(5) |
2455 |
2550 |
4455 |
4550 |
-111 1111(5) |
-111 1111(5) |
-uuu uuuu(5) |
||||
LATE |
2455 |
2550 |
4455 |
4550 |
---- -xxx |
|
---- -uuu |
---- -uuu |
|||
LATD |
2455 |
2550 |
4455 |
4550 |
xxxx xxxx |
|
uuuu uuuu |
uuuu uuuu |
|||
LATC |
2455 |
2550 |
4455 |
4550 |
xx-- -xxx |
|
uu-- -uuu |
uu-- -uuu |
|||
|
|
|
|
|
|
|
|
|
|||
LATB |
2455 |
2550 |
4455 |
4550 |
xxxx xxxx |
|
uuuu uuuu |
uuuu uuuu |
|||
|
|
|
|
|
|
|
|
|
|||
LATA(5) |
2455 |
2550 |
4455 |
4550 |
-xxx xxxx(5) |
|
-uuu uuuu(5) |
-uuu uuuu(5) |
|||
PORTE |
2455 |
2550 |
4455 |
4550 |
0--- x000 |
|
0--- x000 |
u--- uuuu |
|||
PORTD |
2455 |
2550 |
4455 |
4550 |
xxxx xxxx |
|
uuuu uuuu |
uuuu uuuu |
|||
PORTC |
2455 |
2550 |
4455 |
4550 |
xxxx -xxx |
|
uuuu -uuu |
uuuu -uuu |
|||
|
|
|
|
|
|
|
|
|
|||
PORTB |
2455 |
2550 |
4455 |
4550 |
xxxx xxxx |
|
uuuu uuuu |
uuuu uuuu |
|||
|
|
|
|
|
|
|
|
|
|||
PORTA(5) |
2455 |
2550 |
4455 |
4550 |
-x0x 0000(5) |
|
-u0u 0000(5) |
-uuu uuuu(5) |
|||
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
2:One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
3:When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h).
4:See Table 4-3 for Reset value for specific condition.
5:PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’.
DS39632D-page 54 |
Preliminary |
♥ 2007 Microchip Technology Inc. |
PIC18F2455/2550/4455/4550
TABLE 4-4: |
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) |
|||||||||
|
|
|
|
|
|
|
MCLR Resets, |
|
||
Register |
Applicable Devices |
Power-on Reset, |
|
WDT Reset, |
Wake-up via WDT |
|||||
Brown-out Reset |
RESET Instruction, |
or Interrupt |
||||||||
|
|
|
|
|
||||||
|
|
|
|
|
|
|
Stack Resets |
|
||
|
|
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
|
|
UEP15 |
2455 |
2550 |
4455 |
4550 |
---0 0000 |
---0 0000 |
---u uuuu |
|||
|
|
|
|
|
|
|
|
|||
UEP14 |
2455 |
2550 |
4455 |
4550 |
---0 0000 |
---0 0000 |
---u uuuu |
|||
|
|
|
|
|
|
|
|
|||
UEP13 |
2455 |
2550 |
4455 |
4550 |
---0 0000 |
---0 0000 |
---u uuuu |
|||
|
|
|
|
|
|
|
|
|||
UEP12 |
2455 |
2550 |
4455 |
4550 |
---0 0000 |
---0 0000 |
---u uuuu |
|||
|
|
|
|
|
|
|
|
|||
UEP11 |
2455 |
2550 |
4455 |
4550 |
---0 0000 |
---0 0000 |
---u uuuu |
|||
|
|
|
|
|
|
|
|
|||
UEP10 |
2455 |
2550 |
4455 |
4550 |
---0 0000 |
---0 0000 |
---u uuuu |
|||
|
|
|
|
|
|
|
|
|||
UEP9 |
2455 |
2550 |
4455 |
4550 |
---0 0000 |
---0 0000 |
---u uuuu |
|||
|
|
|
|
|
|
|
|
|||
UEP8 |
2455 |
2550 |
4455 |
4550 |
---0 0000 |
---0 0000 |
---u uuuu |
|||
|
|
|
|
|
|
|
|
|||
UEP7 |
2455 |
2550 |
4455 |
4550 |
---0 0000 |
---0 0000 |
---u uuuu |
|||
|
|
|
|
|
|
|
|
|||
UEP6 |
2455 |
2550 |
4455 |
4550 |
---0 0000 |
---0 0000 |
---u uuuu |
|||
|
|
|
|
|
|
|
|
|||
UEP5 |
2455 |
2550 |
4455 |
4550 |
---0 0000 |
---0 0000 |
---u uuuu |
|||
|
|
|
|
|
|
|
|
|||
UEP4 |
2455 |
2550 |
4455 |
4550 |
---0 0000 |
---0 0000 |
---u uuuu |
|||
|
|
|
|
|
|
|
|
|||
UEP3 |
2455 |
2550 |
4455 |
4550 |
---0 0000 |
---0 0000 |
---u uuuu |
|||
|
|
|
|
|
|
|
|
|||
UEP2 |
2455 |
2550 |
4455 |
4550 |
---0 0000 |
---0 0000 |
---u uuuu |
|||
|
|
|
|
|
|
|
|
|||
UEP1 |
2455 |
2550 |
4455 |
4550 |
---0 0000 |
---0 0000 |
---u uuuu |
|||
|
|
|
|
|
|
|
|
|||
UEP0 |
2455 |
2550 |
4455 |
4550 |
---0 0000 |
---0 0000 |
---u uuuu |
|||
|
|
|
|
|
|
|
|
|||
UCFG |
2455 |
2550 |
4455 |
4550 |
00-0 0000 |
00-0 0000 |
uu-u uuuu |
|||
|
|
|
|
|
|
|
|
|||
UADDR |
2455 |
2550 |
4455 |
4550 |
-000 0000 |
-000 0000 |
-uuu uuuu |
|||
|
|
|
|
|
|
|
|
|
||
UCON |
2455 |
2550 |
4455 |
4550 |
-0x0 000- |
|
-0x0 000- |
-uuu uuu- |
||
|
|
|
|
|
|
|
|
|
||
USTAT |
2455 |
2550 |
4455 |
4550 |
-xxx xxx- |
|
-xxx xxx- |
-uuu uuu- |
||
|
|
|
|
|
|
|
|
|||
UEIE |
2455 |
2550 |
4455 |
4550 |
0--0 0000 |
0--0 0000 |
u--u uuuu |
|||
|
|
|
|
|
|
|
|
|||
UEIR |
2455 |
2550 |
4455 |
4550 |
0--0 0000 |
0--0 0000 |
u--u uuuu |
|||
|
|
|
|
|
|
|
|
|||
UIE |
2455 |
2550 |
4455 |
4550 |
-000 0000 |
-000 0000 |
-uuu uuuu |
|||
|
|
|
|
|
|
|
|
|||
UIR |
2455 |
2550 |
4455 |
4550 |
-000 0000 |
-000 0000 |
-uuu uuuu |
|||
|
|
|
|
|
|
|
|
|
||
UFRMH |
2455 |
2550 |
4455 |
4550 |
---- -xxx |
|
---- -xxx |
---- -uuu |
||
|
|
|
|
|
|
|
|
|
||
UFRML |
2455 |
2550 |
4455 |
4550 |
xxxx xxxx |
|
xxxx xxxx |
uuuu uuuu |
||
|
|
|
|
|
|
|
|
|
|
|
SPPCON |
2455 |
2550 |
4455 |
4550 |
---- --00 |
---- --00 |
---- --uu |
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SPPEPS |
2455 |
2550 |
4455 |
4550 |
00-0 0000 |
00-0 0000 |
uu-u uuuu |
|||
SPPCFG |
2455 |
2550 |
4455 |
4550 |
0000 0000 |
0000 0000 |
uuuu uuuu |
|||
SPPDATA |
2455 |
2550 |
4455 |
4550 |
0000 0000 |
0000 0000 |
uuuu uuuu |
|||
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Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
2:One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
3:When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h).
4:See Table 4-3 for Reset value for specific condition.
5:PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’.
♥ 2007 Microchip Technology Inc.
Preliminary
DS39632D-page 55
PIC18F2455/2550/4455/4550
NOTES:
DS39632D-page 56 |
Preliminary |
♥ 2007 Microchip Technology Inc. |