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PIC18F2455/2550/4455/4550

20.4.2EUSART SYNCHRONOUS SLAVE RECEPTION

The operation of the Synchronous Master and Slave modes is identical, except in the case of Sleep, or any Idle mode and bit SREN, which is a “don’t care” in Slave mode.

If receive is enabled by setting the CREN bit prior to entering Sleep or any Idle mode, then a word may be received while in this low-power mode. Once the word is received, the RSR register will transfer the data to the RCREG register. If the RCIE enable bit is set, the interrupt generated will wake the chip from the lowpower mode. If the global interrupt is enabled, the program will branch to the interrupt vector.

To set up a Synchronous Slave Reception:

1.Enable the synchronous master serial port by setting bits SYNC and SPEN and clearing bit CSRC.

2.If interrupts are desired, set enable bit RCIE.

3.If the signal from the CK pin is to be inverted, set the TXCKP bit. If the signal from the DT pin is to be inverted, set the RXDTP bit.

4.If 9-bit reception is desired, set bit RX9.

5.To enable reception, set enable bit CREN.

6.Flag bit, RCIF, will be set when reception is complete. An interrupt will be generated if enable bit, RCIE, was set.

7.Read the RCSTA register to get the 9th bit (if enabled) and determine if any error occurred during reception.

8.Read the 8-bit received data by reading the RCREG register.

9.If any error occurred, clear the error by clearing bit CREN.

10.If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set.

TABLE 20-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION

 

 

 

 

 

 

 

 

 

 

Reset

Name

 

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Values

 

 

 

 

 

 

 

 

 

 

on page

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INTCON

 

GIE/GIEH

PEIE/GIEL

TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

51

PIR1

 

SPPIF(1)

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF

54

PIE1

 

SPPIE(1)

ADIE

RCIE

TXIE

SSPIE

CCP1IE

TMR2IE

TMR1IE

54

IPR1

 

SPPIP(1)

ADIP

RCIP

TXIP

SSPIP

CCP1IP

TMR2IP

TMR1IP

54

RCSTA

 

SPEN

RX9

SREN

CREN

ADDEN

FERR

OERR

RX9D

53

RCREG

 

EUSART Receive Register

 

 

 

 

 

53

 

 

 

 

 

 

 

 

 

 

 

TXSTA

 

CSRC

TX9

TXEN

SYNC

SENDB

BRGH

TRMT

TX9D

53

BAUDCON

ABDOVF

RCIDL

RXDTP

TXCKP

BRG16

WUE

ABDEN

53

SPBRGH

 

EUSART Baud Rate Generator Register High Byte

 

 

 

53

 

 

 

 

 

 

 

SPBRG

 

EUSART Baud Rate Generator Register Low Byte

 

 

 

53

 

 

 

 

 

 

 

 

 

 

 

Legend:

— = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.

 

Note 1:

Reserved in 28-pin devices; always maintain these bits clear.

 

 

 

 

DS39632D-page 258

Preliminary

2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

21.010-BIT ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE

The Analog-to-Digital (A/D) converter module

has

10 inputs for the 28-pin devices and 13 for

the

40/44-pin devices. This module allows conversion of an analog input signal to a corresponding 10-bit digital number.

The module has five registers:

A/D Result High Register (ADRESH)

A/D Result Low Register (ADRESL)

A/D Control Register 0 (ADCON0)

A/D Control Register 1 (ADCON1)

A/D Control Register 2 (ADCON2)

The ADCON0 register, shown in Register 21-1, controls the operation of the A/D module. The ADCON1 register, shown in Register 21-2, configures the functions of the port pins. The ADCON2 register, shown in Register 21-3, configures the A/D clock source, programmed acquisition time and justification.

REGISTER 21-1: ADCON0: A/D CONTROL REGISTER 0

U-0

U-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

 

R/W-0

 

 

 

 

 

 

 

 

 

 

 

 

CHS3

 

CHS2

CHS1

 

CHS0

 

 

 

ADON

GO/DONE

 

bit 7

 

 

 

 

 

 

 

 

 

 

bit 0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Legend:

 

 

 

 

 

 

 

 

 

 

 

R = Readable bit

W = Writable bit

 

U = Unimplemented bit, read as ‘0’

 

 

-n = Value at POR

‘1’ = Bit is set

 

‘0’ = Bit is cleared

 

x = Bit is unknown

 

 

 

 

 

 

 

 

 

 

 

 

bit 7-6

Unimplemented: Read as ‘0

 

 

 

 

 

 

 

 

bit 5-2

CHS3:CHS0: Analog Channel Select bits

 

 

 

 

 

 

 

0000 = Channel 0 (AN0)

0001 = Channel 1 (AN1)

0010 = Channel 2 (AN2)

0011 = Channel 3 (AN3)

0100 = Channel 4 (AN4)

0101 = Channel 5 (AN5)(1,2)

0110 = Channel 6 (AN6)(1,2)

0111 = Channel 7 (AN7)(1,2)

1000 = Channel 8 (AN8)

1001 = Channel 9 (AN9)

1010 = Channel 10 (AN10)

1011 = Channel 11 (AN11)

1100 = Channel 12 (AN12)

1101 = Unimplemented(2)

1110 = Unimplemented(2)

1111 = Unimplemented(2)

bit 1

GO/DONE: A/D Conversion Status bit

 

When ADON = 1:

 

1

= A/D conversion in progress

 

0

= A/D Idle

bit 0

ADON: A/D On bit

 

1

= A/D converter module is enabled

 

0

= A/D converter module is disabled

Note 1: These channels are not implemented on 28-pin devices.

2:Performing a conversion on unimplemented channels will return a floating input measurement.

2007 Microchip Technology Inc.

Preliminary

DS39632D-page 259

PIC18F2455/2550/4455/4550

REGISTER 21-2: ADCON1: A/D CONTROL REGISTER 1

U-0

 

U-0

 

 

 

R/W-0

 

 

 

R/W-0

 

 

R/W-0(1)

 

R/W(1)

 

 

R/W(1)

 

R/W(1)

 

 

 

 

VCFG0

 

 

 

VCFG0

 

PCFG3

 

 

PCFG2

 

 

PCFG1

 

PCFG0

bit 7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

bit 0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Legend:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R = Readable bit

 

 

W = Writable bit

 

 

 

 

U = Unimplemented bit, read as ‘0’

 

 

 

-n = Value at POR

 

 

‘1’ = Bit is set

 

 

 

 

‘0’ = Bit is cleared

 

x = Bit is unknown

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

bit 7-6

 

Unimplemented: Read as ‘0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

bit 5

 

VCFG0: Voltage Reference Configuration bit (VREF- source)

 

 

 

 

 

 

 

 

 

 

 

1 = VREF- (AN2)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0 = VSS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

bit 4

 

VCFG0: Voltage Reference Configuration bit (VREF+ source)

 

 

 

 

 

 

 

 

 

 

 

1 = VREF+ (AN3)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0 = VDD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

bit 3-0

 

PCFG3:PCFG0: A/D Port Configuration Control bits:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCFG0

AN12

 

AN11

 

AN10

 

AN9

 

AN8

 

(2)

(2)

 

 

(2)

 

AN4

AN3

AN2

 

AN1

AN0

 

 

 

 

 

 

 

 

AN7

AN6

 

AN5

 

 

 

 

 

PCFG3:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0000

(1)

A

 

A

 

A

 

A

 

A

 

A

A

 

 

A

 

A

A

A

 

A

A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0001

 

A

 

A

 

A

 

A

 

A

 

A

A

 

 

A

 

A

A

A

 

A

A

 

 

 

0010

 

A

 

A

 

A

 

A

 

A

 

A

A

 

 

A

 

A

A

A

 

A

A

 

 

 

0011

 

D

 

A

 

A

 

A

 

A

 

A

A

 

 

A

 

A

A

A

 

A

A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0100

 

D

 

D

 

A

 

A

 

A

 

A

A

 

 

A

 

A

A

A

 

A

A

 

 

 

0101

 

D

 

D

 

D

 

A

 

A

 

A

A

 

 

A

 

A

A

A

 

A

A

 

 

 

0110

 

D

 

D

 

D

 

D

 

A

 

A

A

 

 

A

 

A

A

A

 

A

A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0111

(1)

D

 

D

 

D

 

D

 

D

 

A

A

 

 

A

 

A

A

A

 

A

A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1000

 

D

 

D

 

D

 

D

 

D

 

D

A

 

 

A

 

A

A

A

 

A

A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1001

 

D

 

D

 

D

 

D

 

D

 

D

D

 

 

A

 

A

A

A

 

A

A

 

 

 

1010

 

D

 

D

 

D

 

D

 

D

 

D

D

 

 

D

 

A

A

A

 

A

A

 

 

 

1011

 

D

 

D

 

D

 

D

 

D

 

D

D

 

 

D

 

D

A

A

 

A

A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1100

 

D

 

D

 

D

 

D

 

D

 

D

D

 

 

D

 

D

D

A

 

A

A

 

 

 

1101

 

D

 

D

 

D

 

D

 

D

 

D

D

 

 

D

 

D

D

D

 

A

A

 

 

 

1110

 

D

 

D

 

D

 

D

 

D

 

D

D

 

 

D

 

D

D

D

 

D

A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1111

 

D

 

D

 

D

 

D

 

D

 

D

D

 

 

D

 

D

D

D

 

D

D

 

 

 

A = Analog input

 

 

 

 

 

 

 

 

D = Digital I/O

 

 

 

 

 

 

 

 

 

 

Note 1: The POR value of the PCFG bits depends on the value of the PBADEN Configuration bit. When PBADEN = 1, PCFG<3:0> = 0000; when PBADEN = 0, PCFG<3:0> = 0111.

2:AN5 through AN7 are available only on 40/44-pin devices.

DS39632D-page 260

Preliminary

2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

REGISTER 21-3: ADCON2: A/D CONTROL REGISTER 2

R/W-0

 

U-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

 

 

 

 

 

 

 

 

 

 

 

ADFM

 

 

ACQT2

 

ACQT1

ACQT0

ADCS2

ADCS1

ADCS0

bit 7

 

 

 

 

 

 

 

 

 

bit 0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Legend:

 

 

 

 

 

 

 

 

 

 

R = Readable bit

 

W = Writable bit

 

U = Unimplemented bit, read as ‘0’

 

-n = Value at POR

 

‘1’ = Bit is set

 

‘0’ = Bit is cleared

x = Bit is unknown

 

 

 

 

 

 

bit 7

ADFM: A/D Result Format Select bit

 

 

 

 

 

1 = Right justified

 

 

 

 

 

 

0 = Left justified

 

 

 

 

 

 

 

bit 6

Unimplemented: Read as ‘0

 

 

 

 

 

bit 5-3

ACQT2:ACQT0: A/D Acquisition Time Select bits

 

 

 

 

111

= 20 TAD

 

 

 

 

 

 

 

 

110

= 16 TAD

 

 

 

 

 

 

 

 

101

= 12 TAD

 

 

 

 

 

 

 

 

100

= 8 TAD

 

 

 

 

 

 

 

 

011

= 6 TAD

 

 

 

 

 

 

 

 

010

= 4 TAD

 

 

 

 

 

 

 

 

001

= 2 TAD

 

 

 

 

 

 

 

 

000

= 0 TAD(1)

 

 

 

 

 

 

 

bit 2-0

ADCS2:ADCS0: A/D Conversion Clock Select bits

 

 

 

 

111

= FRC (clock derived from A/D RC oscillator)(1)

 

 

 

 

110

= FOSC/64

 

 

 

 

 

 

 

 

101

= FOSC/16

 

 

 

 

 

 

 

 

100

= FOSC/4

 

 

 

 

 

 

 

 

011

= FRC (clock derived from A/D RC oscillator)(1)

 

 

 

 

010

= FOSC/32

 

 

 

 

 

 

 

 

001

= FOSC/8

 

 

 

 

 

 

 

 

000

= FOSC/2

 

 

 

 

 

 

 

Note 1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D clock starts. This allows the SLEEP instruction to be executed before starting a conversion.

2007 Microchip Technology Inc.

Preliminary

DS39632D-page 261

PIC18F2455/2550/4455/4550

The analog reference voltage is software selectable to either the device’s positive and negative supply voltage (VDD and VSS) or the voltage level on the RA3/AN3/VREF+ and RA2/AN2/VREF-/CVREF pins.

The A/D converter has a unique feature of being able to operate while the device is in Sleep mode. To operate in Sleep, the A/D conversion clock must be derived from the A/D’s internal RC oscillator.

The output of the sample and hold is the input into the converter, which generates the result via successive approximation.

A device Reset forces all registers to their Reset state. This forces the A/D module to be turned off and any conversion in progress is aborted.

Each port pin associated with the A/D converter can be configured as an analog input or as a digital I/O. The ADRESH and ADRESL registers contain the result of the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRESH:ADRESL register pair, the GO/DONE bit (ADCON0 register) is cleared and A/D Interrupt Flag bit, ADIF, is set. The block diagram of the A/D module is shown in Figure 21-1.

FIGURE 21-1:

A/D BLOCK DIAGRAM

 

 

 

 

 

CHS3:CHS0

 

 

 

 

1100

 

 

 

 

AN12

 

 

 

 

1011

 

 

 

 

AN11

 

 

 

 

1010

 

 

 

 

AN10

 

 

 

 

1001

 

 

 

 

AN9

 

 

 

 

1000

 

 

 

 

AN8

 

 

 

 

0111

 

 

 

 

AN7(1)

 

 

 

 

0110

 

 

 

 

AN6(1)

 

 

 

 

0101

 

 

 

 

AN5(1)

 

 

 

 

0100

 

 

 

VAIN

AN4

 

 

 

 

 

10-Bit

 

(Input Voltage)

0011

 

 

AN3

Converter

 

 

 

 

A/D

 

 

0010

 

 

 

 

AN2

 

 

 

VCFG1:VCFG0

0001

 

 

 

AN1

 

 

 

VDD(2)

0000

 

 

 

 

AN0

 

 

VREF+

X0

 

 

Reference

X1

 

 

 

1X

 

 

Voltage

VREF-

 

 

0X

 

 

 

 

 

 

 

 

 

 

 

 

VSS(2)

Note 1: Channels AN5 through AN7 are not available on 28-pin devices.

2:I/O pins have diode protection to VDD and VSS.

DS39632D-page 262

Preliminary

2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

The value in the ADRESH:ADRESL registers is not modified for a Power-on Reset. The ADRESH:ADRESL registers will contain unknown data after a Power-on Reset.

5.Wait for A/D conversion to complete, by either:

• Polling for the GO/DONE bit to be cleared

OR

After the A/D module has been configured as desired,

 

 

• Waiting for the A/D interrupt

 

 

 

 

6.

 

Read A/D Result registers (ADRESH:ADRESL);

the selected channel must be acquired before the con-

 

 

 

clear bit ADIF, if required.

 

 

 

 

version is started. The analog input channels must

 

 

 

 

 

 

7.

For next conversion, go to step 1 or step 2, as

have their corresponding TRIS bits selected as an

input. To determine acquisition time, see Section 21.1

 

 

required. The A/D conversion time per bit is

“A/D Acquisition Requirements”. After this acquisi-

 

 

defined as TAD. A minimum wait of 3 TAD is

tion time has elapsed, the A/D conversion can be

 

 

required before the next acquisition starts.

 

 

started. An acquisition time can be programmed to

 

 

 

 

 

 

 

 

 

 

 

 

occur between setting the GO/DONE bit and the actual

FIGURE 21-2:

 

A/D TRANSFER FUNCTION

start of the conversion.

 

 

 

 

 

 

 

 

 

 

 

 

 

The following steps should be followed to perform an

 

 

3FFh

 

 

 

 

 

 

 

 

 

A/D conversion:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1.

Configure the A/D module:

 

 

Output

3FEh

 

 

 

 

 

 

 

 

 

 

digital I/O (ADCON1)

 

 

 

 

 

 

 

 

 

 

 

 

 

Configure analog pins, voltage reference and

 

 

 

 

 

 

 

 

 

 

 

 

 

Select A/D input channel (ADCON0)

 

 

Code

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

• Select A/D acquisition time (ADCON2)

 

 

Digital

003h

 

 

 

 

 

 

 

 

 

 

Select A/D conversion clock (ADCON2)

 

 

002h

 

 

 

 

 

 

 

 

 

 

Turn on A/D module (ADCON0)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2.

Configure A/D interrupt (if desired):

 

 

 

001h

 

 

 

 

 

 

 

 

 

 

Clear ADIF bit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Set ADIE bit

 

 

 

 

000h

LSB

 

LSB

 

LSB

LSB

 

LSB

 

4.

Set GIE bit

 

 

 

 

LSB

LSB

LSB

LSB

LSB

Start conversion:

 

 

 

 

0.5

1

1.5

2

2.5

3

1022

1022.5

1023

1023.5

3.

Wait the required acquisition time (if required).

 

 

 

 

 

 

 

 

 

 

 

 

 

Set GO/DONE bit (ADCON0 register)

 

 

 

 

 

 

Analog Input Voltage

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FIGURE 21-3:

ANALOG INPUT MODEL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VDD

 

 

 

 

Sampling

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VT = 0.6V

 

 

 

Switch

 

 

 

 

 

 

 

 

 

 

ANx

 

 

 

SS

 

 

 

 

 

 

 

 

 

 

Rs

 

 

RIC ≤ 1k

RSS

 

 

 

 

 

 

 

 

VAIN

CPIN

 

ILEAKAGE

 

 

 

 

CHOLD = 25 pF

 

 

 

 

 

5 pF

VT = 0.6V

 

 

 

 

 

 

 

 

 

 

±100 nA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VSS

 

 

 

 

Legend: CPIN

= Input Capacitance

 

 

 

 

 

 

 

 

 

 

 

 

 

VT

= Threshold Voltage

 

6V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ILEAKAGE

= Leakage Current at the pin due to

VDD

5V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4V

 

 

 

 

 

 

 

 

 

 

 

 

various junctions

 

 

 

 

 

 

 

 

 

 

 

 

 

3V

 

 

 

 

 

 

 

 

 

 

 

RIC

= Interconnect Resistance

 

 

 

 

 

 

 

 

 

 

 

 

 

2V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SS

= Sampling Switch

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CHOLD

= Sample/hold Capacitance (from DAC)

 

1 2 3 4

 

RSS

= Sampling Switch Resistance

 

 

 

 

Sampling Switch (kΩ)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2007 Microchip Technology Inc.

Preliminary

DS39632D-page 263

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