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PIC18F2455/2550/4455/4550

18.3.3READING FROM THE SPP

Reading from the SPP involves reading the SPPDATA register. Reading the register the first time initiates the read operation. When the read is finished, indicated by the SPPBUSY bit, the SPPDATA will be loaded with the current data.

The following is an example read sequence:

1.Write the 4-bit address to the SPPEPS register. The SPP automatically starts writing the address. If address write is not used then skip to step 3.

2.Monitor the SPPBUSY bit to determine when the address has been sent. The duration depends on the wait states.

3.Read the data from the SPPDATA register; the data from the previous read operation is returned. The SPP automatically starts the read cycle for the next read.

4.Monitor the SPPBUSY bit to determine when the data has been read. The duration depends on the wait states.

5.Go back to step 3 to read the current byte from the SPP and start the next read cycle.

REGISTER 18-3: SPPEPS: SPP ENDPOINT ADDRESS AND STATUS REGISTER

R-0

 

R-0

U-0

R-0

R/W-0

R/W-0

R/W-0

R/W-0

 

 

 

 

 

 

 

 

 

 

 

RDSPP

 

WRSPP

 

SPPBUSY

 

ADDR3

ADDR2

ADDR1

ADDR0

bit 7

 

 

 

 

 

 

 

 

 

bit 0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Legend:

 

 

 

 

 

 

 

 

 

 

R = Readable bit

 

W = Writable bit

U = Unimplemented bit, read as ‘0’

 

-n = Value at POR

‘1’ = Bit is set

 

 

‘0’ = Bit is cleared

x = Bit is unknown

 

 

 

bit 7

RDSPP: SPP Read Status bit (Valid when SPPCON<SPPOWN> = 1, USB)

 

 

1

= The last transaction was a read from the SPP

 

 

 

 

0

= The last transaction was not a read from the SPP

 

 

 

bit 6

WRSPP: SPP Write Status bit (Valid when SPPCON<SPPOWN> = 1, USB)

 

 

1

= The last transaction was a write to the SPP

 

 

 

 

0

= The last transaction was not a write to the SPP

 

 

 

bit 5

Unimplemented: Read as ‘0

 

 

 

 

 

 

bit 4

SPPBUSY: SPP Handshaking Override bit

 

 

 

 

 

1

= The SPP is busy

 

 

 

 

 

 

 

0

= The SPP is ready to accept another read or write request

 

 

bit 3-0

ADDR3:ADDR0: SPP Endpoint Address bits

 

 

 

 

1111 = Endpoint Address 15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0001

 

 

 

 

 

 

 

 

0000 = Endpoint Address 0

2007 Microchip Technology Inc.

Preliminary

DS39632D-page 191

PIC18F2455/2550/4455/4550

TABLE 18-1: REGISTERS ASSOCIATED WITH THE STREAMING PARALLEL PORT

 

 

 

 

 

 

 

 

 

 

Reset

Name

 

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Values

 

 

 

 

 

 

 

 

 

 

on page

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SPPCON(3)

SPPOWN

SPPEN

55

SPPCFG(3)

CLKCFG1

CLKCFG0

CSEN

CLK1EN

WS3

WS2

WS1

WS0

55

SPPEPS(3)

RDSPP

WRSPP

SPPBUSY

ADDR3

ADDR2

ADDR1

ADDR0

55

SPPDATA(3)

DATA7

DATA6

DATA5

DATA4

DATA3

DATA2

DATA1

DATA0

55

PIR1

 

SPPIF(3)

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF

54

PIE1

 

SPPIE(3)

ADIE

RCIE

TXIE

SSPIE

CCP1IE

TMR2IE

TMR1IE

54

IPR1

 

SPPIP(3)

ADIP

RCIP

TXIP

SSPIP

CCP1IP

TMR2IP

TMR1IP

54

PORTE

 

RDPU(3)

RE3(1,2)

RE2(3)

RE1(3)

RE0(3)

54

Legend:

— = unimplemented, read as ‘0’. Shaded cells are not used for the Streaming Parallel Port.

 

Note 1:

Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0).

 

2:RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are implemented only when PORTE is implemented (i.e., 40/44-pin devices).

3:These registers and/or bits are unimplemented on 28-pin devices.

DS39632D-page 192

Preliminary

2007 Microchip Technology Inc.

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