10 - 13
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CHUNG-YU WU |
V = V |
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+ I R = V |
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ln A* + V ) |
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out |
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BE 3 |
3 2 |
BE 3 |
3 R q |
sg |
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1 |
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2. |
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A |
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Cst
3. Type B structure
10 - 14
CHUNG-YU WU
4.Type C structure
The cascode structure of BVR (Type C):
The variation of Vsg versus temperature
10 - 15
CHUNG-YU WU
The simulated output voltages versus temperature in Type A and Type A BVR
The variation of Vsg versus MOS channel length in Type A BVR
10 - 16
CHUNG-YU WU
The Spice simulated output voltages versus temperature in Type C BVR
The measured output voltages versus temperature in the fabricared cascaded-structure BVR(Type C)[ 3.5 ìm CMOS technology , R1=1KÙ(external),R2=25.9KÙ(external)]
10 - 17
CHUNG-YU WU
* Average temperature drift |
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5.5 ppm/oC |
-60 oC ~ +150 oC |
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5V~15V |
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At 25 oC, average voltage drift 25ìV/V |
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Vout=1.1963V |
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1.1965V |
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2 mil2 , 0.8 mW at 5V |
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§10-5 CMOS Bandgap Reference with Sub-1-V Operation
Ref.: IEEE JSSC, vol.34, pp.670~674, May 1999
Concept: * Convertional BGR Vref = 1.25V
Can’t be operated below 1V supply. |
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* The built-in voltage |
V f of the diode → |
the current I2b |
The thermal voltage |
Vtherm → the current |
I2a |
(I2a + I 2b )R → Vref |
< 1V |
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1.Schematic of the proposed BGR
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Vf1 |
I2a |
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Vf2 |
I2b R4 |
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I1b |
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Native NMOS VTHI = −0.2V
NMOS VTHN = +0.7V
PMOS VTHP = −1.0V
10 - 18
CHUNG-YU WU
*The diode is realized by the parasitic P + / n − well / P − substract BJT as
*C1 and C 2 are used to stabilized the circuit.
*The control signal PONRST is used to initialize the BGR circuit when the power
is turned on. |
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* R1 |
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Va |
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I1 = I2 |
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dV f = V f 1 − V f 2 = Vtherm ln(N ) |
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N = 100 |
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Vtherm |
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I2b |
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I3 = I 2 = I2a + I2b |
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Vref |
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2. Simulated |
Vref characteristics |
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VDD
10 - 19
CHUNG-YU WU
*Vref |
= 1.25V |
conventional BGR |
*Vref |
= 0.84V |
proposed BGR |
3.Minimum VDD
min V1 @ Vs @ Vb -VTHI @ V f + VTHI @ VDD +VTHP = minVDD - VTHP
Þmin VDD = V f + VTHI + VTHP @ 0.8 ~ 1.0V
0.54-0.2 -0.3
4.Measured results:
VDD
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VDD |
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*TC @ 60 ppm / O C |
27O ~ 125O C |
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Voltage drift (average) |
@ 600μV /V |
2.2V~4V |
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11-1
CHUNG-YU WU
CH 11 Digital-to-Analog Converters (DACs) in CMOS
Technology
§11-1 Introduction
1. Block diagram
Analog Signal |
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Analog |
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Filtering |
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D/A |
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Sensor.....) |
Digital |
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Conversion |
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and A/D |
Processing |
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Conversion |
and Filtering |
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Control |
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Analog World |
Digital World |
Analog World |
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(Digital signal processing has better noise immunity than analog signal processing.)
Fig. 11.1 A block diagram of a typical signal processing system
Digital |
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Control
Fig. 11.2 Functional block diagram of a D/A converte
11-2
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CHUNG-YU WU |
2. Ideal DAC: |
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Analog output signal Vout = Vref (b 2-1+b |
2-2+ ---- +b 2-N) |
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2 |
N |
Vref: analog reference signal
b1 … … . bN : N-bit digital data input
The signal change when one LSB changes is VLSB
VLSB ≡ Vref
2 N
If in LSB unit, 1LSB= 1 2N
3.DAC performance specifications
(1)Resolution: The number of distinct analog levels corresponding to the
different digital words.
N-bit resolution → 2Ndistinct analog levels.
(2) Offset error:
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Eoff (DAC) ≡ |
Vout |
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(3) Gain error: |
VLSB |
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Egain (DAC) ≡ [ |
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Offset |
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Eoff(DAC) |
set to zero |
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0......0 |
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1......1 |
Digital Data |
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Input Bin