Getting Started and Creating Applications |
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Chapter 10. CPU and C Startup Code
The STARTUP.A51 file contains the startup code for a C51 target program. This |
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source file is located in the LIB directory. Include a copy of this file in each |
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8051 project that needs custom startup code. |
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This code is executed immediately upon reset of the target system and optionally |
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performs the following operations, in order: |
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Clears internal data memory |
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Clears external data memory |
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Clears paged external data memory |
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Initializes the small model reentrant stack and pointer |
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Initializes the large model reentrant stack and pointer |
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Initializes the compact model reentrant stack and pointer |
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Initializes the 8051 hardware stack pointer |
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Transfers control to the main C function |
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The STARTUP.A51 file provides you with assembly constants that you may change to control the actions taken at startup. These are defined in the following table.
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Description |
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IDATALEN |
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Indicates the number of bytes of idata that are to be initialized to 0. |
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The default is 80h because most 8051 derivatives contain at least |
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128 bytes of internal data memory. Use a value of 100h for the |
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8052 and other derivatives that have 256 bytes of internal data |
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memory. |
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XDATASTART |
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Specifies the xdata address to start initializing to 0. |
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XDATALEN |
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Indicates the number of bytes of xdata to be initialized to 0. |
The |
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default is 0. |
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PDATASTART |
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Specifies the pdata address to start initializing to 0. |
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PDATALEN |
Indicates the number of bytes of pdata to be initialized to 0. |
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default is 0. |
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IBPSTACK |
Indicates whether or not the small model reentrant stack pointer |
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(?C_IBP) should be initialized. A value of 1 causes this pointer to |
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be initialized. A value of 0 prevents initialization of this pointer. The default is 0.
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Chapter 10. CPU and C Startup Code |
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Constant Name |
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IBPSTACKTOP |
Specifies the top start address of the small model reentrant stack |
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area. The default is 0xFF in idata memory. |
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C51 does not check to see if the stack area available satisfies the |
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requirements of the applications. It is your responsibility to perform |
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such a test. |
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XBPSTACK |
Indicates whether or not the large model reentrant stack pointer |
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(?C_XBP) should be initialized. A value of 1 causes this pointer to |
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be initialized. A value of 0 prevents initialization of this pointer. The |
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default is 0. |
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XBPSTACKTOP |
Specifies the top start address of the large model reentrant stack |
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area. The default is 0xFFFF in xdata memory. |
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C51 does not check to see if the available stack area satisfies the |
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requirements of the applications. It is your responsibility to perform |
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such a test. |
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PBPSTACK |
Indicates whether the compact model reentrant stack pointer |
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(?C_PBP) should be initialized. A value of 1 causes this pointer to |
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be initialized. A value of 0 prevents initialization of this pointer. The |
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default is 0. |
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PBPSTACKTOP |
Specifies the top start address of the compact model reentrant stack |
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area. The default is 0xFF in pdata memory. |
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C51 does not check to see if the available stack area satisfies the |
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requirements of the applications. It is your responsibility to perform |
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such a test. |
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PPAGEENABLE |
Enables (a value of 1) or disables (a value of 0) the initialization of |
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port 2 of the 8051 device. The default is 0. The addressing of port 2 |
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allows the mapping of 256 byte variable memory in any arbitrary |
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xdata page. |
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PPAGE |
Specifies the value to write to Port 2 of the 8051 for pdata memory |
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access. This value represents the xdata memory page to use for |
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pdata. This is the upper 8 bits of the absolute address range to use |
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for pdata. |
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For example, if the pdata area begins at address 1000h (page 10h) |
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in the xdata memory, PPAGEENABLE should be set to 1, and |
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PPAGE should be set to 10h. The BL51 Linker/Locator must |
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contain a value between 1000h and 10FFh in the PDATA control |
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directive. For example: |
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BL51 <input modules> PDATA (1050H) |
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Neither BL51 nor C51 checks to see if the PDATA control directive |
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and the PPAGE assembler constant are correctly specified. You |
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must ensure that these parameters contain suitable values. |
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Getting Started and Creating Applications |
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Chapter 11. Using Monitor-51
The Keil Monitor-51 allows you to debug programs on your target hardware using the µVision2 Debugger. You connect the µVision2 Debugger to your 8051 target board using a serial cable.
To get started, you must properly configure and install Monitor-51 on your target hardware. Configuration and installation of the Monitor is explained in the file
\KEIL\C51\MON51\MON51.PDF.
Caveats |
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There are only a few drawbacks to using Monitor-51.
The Monitor requires that programs you debug are located in RAM space. This is required because breakpoints are set by replacing instructions in your program with an ACALL instruction. This operation, while completely transparent, may have side-effects that affect the operation of your target program. Refer to “Breakpoint Side Effects” on page 203 for more information.
You will most likely have to relocate your startup code, program code segments, and interrupt vector table.
You may enable or disable the HALT command on the toolbar in µVision2 Debugger. If you enable this feature, using Stop Program Execution with Serial Interrupt check box under Options – Debug – Keil Monitor-51 Driver Settings, the µVision2 Debugger and the monitor use the 8051 serial interrupt vector to signal that the target program should stop running.
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Chapter 11. Using Monitor-51 |
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Hardware and Software Requirements
The following requirements must be met for Monitor-51 to operate correctly.
The CPU must be an 8051 or derivative.
The monitor requires 5 Kbyte external code memory (EPROM) starting at address 0.
256 Bytes of external data memory (XDATA RAM) is required. 5 Kbytes of trace buffer is optional. You must have enough external data memory to hold
the complete application (code and data). All external data memory areas must be von Neumann wired—access must be possible from XDATA and 11 CODE space. A common way to do this is to connect the /PSEN and /RD
CPU signals to the inputs of an AND gate and the output of the AND gate to the /RD pin of the RAM.
The monitor uses a serial interface with a timer as the baudrate generator.
Between 1 and 5 port pins are necessary if you use banked hardware (for 2-32 banks). For details on banking hardware, refer to the example hardware schematics in the 8051 Utilities User’s Guide, Chapter 1 “Bank Switching Configuration”. All memory banks must be von Neumann wired.
The monitor uses an additional 6 bytes of stack space (IDATA) in the user program to be tested.
All other hardware components can be used by the application.