Fundamentals of Microelectronics

14.An inverting amplifier employs an op amp having an output impedance of Rout. Modeling the op amp as depicted in Fig. 8.44, compute the closed-loop gain and output impedance.

15.An inverting amplifier must provide an input impedance of approximately 10 k and a nominal gain of 4. If the op amp exhibits an open-loop gain of 1000 and an output impedance of

1k , determine the gain error.

16.An inverting amplifier is designed for a nominal gain of 8 and a gain error of 0:1% using an op amp that exhibits an output impedance of 2 k . If the input impedance of the circuit must be equal to approximately 1 k , calculate the required open-loop gain of the op amp.

17.Assuming A0 = 1, compute the closed-loop gain of the inverting amplifier shown in Fig.

8.49.Verify that the result reduces to expected values if R1 ! 0 or R3 ! 0.

R3 R1

R4

R2

Vout

Vin

Figure 8.49

18. Determine the closed-loop gain of the circuit depicted in Fig. 8.50 if A0 = 1.

R1

Figure 8.50

19. The integrator of Fig. 8.51 senses an input signal given by Vin = V0 sin !t. Determine the

C1

R1

Vin

Figure 8.51

output signal amplitude if A0 = 1.

20.The integrator of Fig. 8.51 is used to amplify a sinusoidal input by a factor of 10. If A0 = 1 and R1C1 = 10 ns, compute the frequency of the sinusoid.

21.The integrator of Fig. 8.51 must provide a pole at no higher than 1 Hz. If the values of R1 and C1 are limited to 10 k and 1 nF, respectively, determine the required gain of the op amp.

22.Consider the integrator shown in Fig. 8.51 and suppose the op amp is modeled as shown in Fig. 8.43. Determine the transfer function Vout=Vin and compare the location of the pole with that given by Eq. (8.37).

23.The op amp used in the integrator of Fig. 8.51 exhibits a finite output impedance and is modeled as depicted in Fig. 8.44. Compute the transfer function Vout=Vin and compare the location of the pole with that given by Eq. (8.57).

24.The differentiator of Fig. 8.52 is used to amplify a sinusoidal input at a frequency of 1 MHz

R1

C1

Vin

Figure 8.52

by a factor of 5. If A0 = 1, determine the value of R1C1.

25.We wish to design the differentiator of Fig. 8.52 for a pole frequency of 100 MHz. If the values of R1 and C1 cannot be lower than 1 k and 1 nF, respectively, compute the required gain of the op amp.

26.Suppose the op amp in Fig. 8.52 exhibits a finite input impedance and is modeled as shown in Fig. 8.43. Determine the transfer function Vout=Vin and compare the result with Eq. (8.42).

27.The op amp used in the differentiator of Fig. 8.52 suffers from a finite output impedance and is modeled as depicted in Fig. 8.44. Compute the transfer function and compare the result with Eq. (8.42).

28.Calculate the transfer function of the circuit shown in Fig. 8.53 if A0 = 1. What choice of component values reduces jVout=Vinj to unity at all frequencies?

Figure 8.53

29.Repeat Problem 28 if A0 < 1. Can the resistors and capacitors be chosen so as to reduce jVout=Vinj to approximately unity?

30.Consider the voltage adder shown in Fig. 8.54. Plot Vout as a function of time if V1 =

Figure 8.54

V0 sin !t and V2 = V0 sin(3!t). Assume R1 = R2 and A0 = 1.

31.The op amp in Fig. 8.54 suffers from a finite gain. Calculate Vout in terms of V1 and V2.

32.Due to a manufacturing error, a parasitic resistance RP has appeared in the adder of Fig. 8.55. Calculate Vout in terms of V1 and V2 for A0 = 1 and A0 < 1. (Note that RP can

Figure 8.55

also represent the input impedance of the op amp.)

33. The voltage adder of Fig. 8.54 employs an op amp having a finite output impedance, Rout. Using the op amp model depicted in Fig. 8.44, compute Vout in terms of V1 and V2.

34. Consider the voltage adder illustrated in Fig. 8.56, where RP is a parasitic resistance and the

RF

Figure 8.56

op amp exhibits a finite input impedance. With the aid of the op amp model shown in Fig. 8.43, determine Vout in terms of V1 and V2.

35.Plot the current flowing through D1 in the precision rectifier of Fig. 8.22(b) as a function of time for a sinusoidal input.

36.Plot the current flowing through D1 in the precision rectifier of Fig. 8.23(a) as a function of time for a sinusoidal input.

37.Figure 8.57 shows a precision rectifier producing negative cycles. Plot VY , Vout, and the

Figure 8.57

current flowing through D1 as a function of time for a sinusoidal input.

38.Consider the precision rectifier depicted in Fig. 8.58, where a parasitic resistor RP has appeared in parallel with D1. Plot VX and VY as a function of time in response to a sinusoidal input. Use a constant-voltage model for the diode.

39.We wish to improve the speed of the rectifier shown in Fig. 8.22(b) by connecting a diode from node Y to ground. Explain how this can be accomplished.

40.Suppose Vin in Fig. 8.24 varies from ,1 V to +1 V. Sketch Vout and VX as a function of Vin if the op amp is ideal.

414 Chap. 8 Operational Amplifier As A Black Box

Vout

D 1

R P

R1

Figure 8.58

41.Suppose the gain of the op amp in Fig. 8.24 is finite. Determine the input/output characteristic of the circuit.

42.A student attempts to construct a noninverting logarithmic amplifier as illustrated in Fig. 8.59. Describe the operation of this circuit.

Q 1

R1 X

Vout

Vin

Figure 8.59

43.Determine the small-signal voltage gain of the logarithmic amplifier depicted in Fig. 8.24 by differentiating both sides of (8.66) with respect to Vin. Plot the magnitude of the gain as a function of Vin and explain why the circuit is said to provide a “compressive” characteristic.

44.The logarithmic amplifier of Fig. 8.24 must “map” an input range of 1 V to 10 V to an output range of ,1 V to ,1:5 V.

(a)Determine the required values of IS and R1.

(b)Calculate the small-signal voltage gain at the two ends of the range.

45.The circuit illustrated in Fig. 8.60 can be considered a “true” square-root amplifier. Deter-

M 1

R1 X

Vout

Vin VTH

Figure 8.60

mine Vout in terms of Vin and compute the small-signal gain by differentiating the result with respect to Vin.

46.Calculate Vout in terms of Vin for the circuit shown in Fig. 8.61.

47.In the noninverting amplifier of Fig. 8.62, the op amp offset is represented by a voltage source in series with the inverting input. Calculate Vout.

48.Suppose each op amp in Fig. 8.28 suffers from an input offset of 3 mV. Determine the maximum offset error in Vout if each amplifier is designed for a gain of 10.

Figure 8.63

input offset of Vos. Assume A0 = 1.

50.The integrator of Fig. 8.29(c) must operate with frequencies as low as 1 kHz while providing an output offset of less than 20 mV with an op amp offset of 3 mV. Determine the required values of R1 and R2 if C1 100 pF.

51.Explain why dc offsets are not considered a serious issue in differentiators.

52.Explain the effect of op amp offset on the output of a logarithmic amplifier.

53.Suppose the input bias currents in Fig. 8.31 incur a small offset, i.e., IB1 = IB2 + I. Calculate Vout.

54.Repeat Problem 53 for the circuit shown in Fig. 8.33. What is the maximum allowable value of R1jjR2 if the output error due to this mismatch must remain below a certain value, V ?

55.A noninverting amplifier must provide a bandwidth of 100 MHz with a nominal gain of 4. Determine which one of the following op amp specifications are adequate:

(a) A0 = 1000, f1 = 50 Hz.

(a) A0 = 500, f1 = 1 MHz.

56.An inverting amplifier incorporates an op amp whose frequency response is given by Eq. (8.84). Determine the transfer function of the closed-loop circuit and compute the bandwidth.

57.Figure 8.64 shows an integrator employing an op amp whose frequency response is given by

Determine the transfer function of the overall integrator. Simplify the result if !0

1=(R1C1).

Figure 8.64

58.A noninverting amplifier with a nominal gain of 4 senses a sinusoid having a peak amplitude of 0.5 V. If the op amp provides a slew rate of 1 V/ns, what is the highest input frequency for which no slewing occurs?

59.The unity-gain buffer of Fig. 8.3 must be designed to drive a 100 load with a gain error of 0:5%. Determine the required op amp gain if the op amp has an output resistance of 1 k .

Design Problems

60.Design a noninverting amplifier with a nominal gain of 4, a gain error of 0:2%, and a total resistance of 20 k . Assume the op amp has a finite gain but is otherwise ideal.

61.Design the inverting amplifier of Fig. 8.7(a) for a nominal gain of 8 and a gain error of 0:1%. Assume Rout = 100 .

62.Design an integrator that attenuates input frequencies above 100 kHz and exhibits a pole at 100 Hz. Assume the largest available capacitor is 50 pF.

63.With a finite op amp gain, the step response of an integrator is a slow exponential rather than an ideal ramp. Design an integrator whose step response approximates V (t) = t with an error less than 0:1% for the range 0 < V (t) < V0 (Fig. 8.65). Assume = 10 V= s, V0 = 1

Figure 8.65

V, and the capacitor must remain below 20 pF.

64.A voltage adder must realize the following function: Vout = 1V1 + 2V2, where 1 = ,0:5 and 2 = ,1:5. Design the circuit if the worst-case error in 1 or 2 must remain below 0:5% and the input impedance seen by V1 or V2 must exceed 10 k .

65. Design a logarithmic amplifier that “compresses” an input range of [0:1 V 2 V] to an output range of [,0:5 V , 1 V].

66.Can a logarithmic amplifier be designed to have a small-signal gain ( dVout=dVin) of 2 at

Vin = 1 V and 0.2 at Vin = 2 V? Assume the gain of the op amp is sufficiently high.

SPICE Problems

67.Assuming an op amp gain of 1000 and IS = 10,17 A for D1, plot the input/output characteristic of the precision rectifier shown in Fig. 8.66.

Vin Y

Figure 8.66

68.Repeat Problem 67 but assuming that the op amp suffers from an output resistance of 1 k .

69.In the circuit of Fig. 8.67, each op amp provides a gain of 500. Apply a 10-MHz sinusoid at the input and plot the output as a function of time. What is the error in the output amplitude with respect to the input amplitude?

Figure 8.67

70. Using ac analysis in SPICE, plot the frequency response of the circuit depicted in Fig. 8.68.

Figure 8.68

71.The arrangement shown in Fig. 8.69 incorporates an op amp to “linearize” a common-emitter stage. Assume IS;Q1 = 5 10,16 A, and = 100.

VCC = 2.5 V 500Ω

Vout

Q 1

Vin

X 100Ω

Figure 8.69

(a) Explain why the small-signal gain of the circuit approaches RC =RE if the gain of the op amp is very high. (Hint: VX Vin.)

(b)Plot the input/output characteristic of the circuit for 0:1 V < Vin < 0:2 V and an op amp gain of 100.

(c)Subtract Vout = 5Vin (e.g., using a voltage-dependent voltage source) from the above characteristic and determine the maximum error.

Cascode Stages and Current

Mirrors

Following our study of basic bipolar and MOS amplifiers in previous chapters, we deal with two other important building blocks in this chapter. The “cascode” 1 stage is a modified version of common-emitter or common-source topologies and proves useful in high-performance circuit design, and the “current mirror” is an interesting and versatile technique employed extensively in integrated circuits. Our study includes both bipolar and MOS implementations of each building block. Shown below is the outline of the chapter.

9.1 Cascode Stage

9.1.1 Cascode as a Current Source

Recall from Chapters 5 and 7 that the use of current-source loads can markedly increase the voltage gain of amplifiers. We also know that a single transistor can operate as a current source but its output impedance is limited due to the Early effect (in bipolar devices) or channel-length modulation (in MOSFETs).

How can we increase the output impedance of a transistor that acts as a current source? An important observation made in Chapters 5 and 7 forms the foundation for our study here: emitter or source degeneration “boosts” the impedance seen looking into the collector or drain, respectively. For the circuits shown in Fig. 9.1, we have

Figure 9.1 Output impedance of degenerated bipolar and MOS devices.

1Coined in the vacuum-tube era, the term “cascode” is believed to be an abbreviation of “cascaded triodes.”

419

observing that RE or RS can be increased to raise the output resistance. Unfortunately, however, the voltage drop across the degeneration resistor also increases proportionally, consuming voltage headroom and ultimately limiting the voltage swings provided by the circuit using such a current source. For example, if RE sustains 300 mV and Q1 requires a minimum collectoremitter voltage of 500 mV, then the degenerated current source “`consumes” a headroom of 800 mV.

Bipolar Cascode In order to relax the trade-off between the output impedance and the voltage headroom, we can replace the degeneration resistor with a transistor. Depicted in Fig. 9.2(a) for the bipolar version, the idea is to introduce a high small-signal resistance (= rO2) in the

Figure 9.2 (a) Cascode bipolar current source, (b) equivalent circuit.

emitter of Q1 while consuming a headroom independent of the current. In this case, Q2 requires a headroom of approximately 0.4 V to remain soft saturation. This configuration is called the “cascode” stage. 2 To emphasize that Q1 and Q2 play distinctly different roles here, we call Q1 the cascode transistor and Q2 the degeneration transistor. Note thatIC1 IC2 if 1 1.

Let us compute the output impedance of the bipolar cascode of Fig. 9.2(a). Since the baseemitter voltage of Q2 is constant, this transistor simply operates as a small-signal resistance equal to rO2 [Fig. 9.2(b)]. In analogy with the resistively-degenerated counterpart in Fig. 9.1, we have

Note, however, that rO cannot generally be assumed much greater than r .

Example 9.1

If Q1 and Q2 in Fig. 9.2(a) are biased at a collector current of 1 mA, determine the output resistance. Assume = 100 and VA = 5 V for both transistors.

2Or simply the “cascode.”