Fundamentals of Microelectronics

R out

Vb1Q 1

Vb2

Q 2

Figure 9.44

(a)Assuming both transistors operate in the active region, determine the output impedance of the circuit.

(b)Compare the result with that of a cascode stage for a given bias current (IC1) and explain why this is generally not a good idea.

9.For discrete bipolar transistors, the Early voltage reaches tens of volts, allowing the approximation VA VT if < 100. Using this approximation, simplify Eq. (9.9) and explain why the result resembles that in Eq. (9.12).

10.The pnp cascode depicted in Fig. 9.45 must provide a bias current of 0.5 mA to a circuit. If

VCC = 2.5 V

Vb2 Q 2

X

Vb1 Q 1

Circuit

0.5 mA

Figure 9.45

IS = 10,16 and = 100,

(a)Calculate the required value of Vb2.

(b)Noting that VX = Vb1 + jVBE1j, determine the maximum allowable value of Vb1 such that Q2 experiences a base-collector forward bias of only 200 mV.

11.Determine the output impedance of each circuit shown in Fig. 9.46. Assume 1. Explain which ones are considered cascode stages.

12.The MOS cascode of Fig. 9.47 must provide a bias current of 0.5 mA with an output impedance of at least 50 k . If nCox = 100 A/V2 and W=L = 20=0:18 for both transistors, compute the maximum tolerable value of .

13.(a) Writing gm = p2 nCox(W=L)ID, express Eq. (9.23) in terms of ID and plot the result as a function of ID.

(b)Compare this expression with that in Eq. (9.9) for the bipolar counterpart. Which one is a stronger function of the bias current?

14.The cascode current source shown in Fig. 9.48 must be designed for a bias current of 0.5 mA. Assume nCox = 100 A/V2 and VTH = 0:4 V.

(a)Neglecting channel-length modulation, compute the required value of Vb2. What is the minimum tolerable value of Vb1 if M2 must remain in saturation?

(b)Assuming = 0:1 V,1, calculate the output impedance of the circuit.

15.Consider the circuit shown in Fig. 9.49, where VDD = 1:8 V, (W=L)1 = 20=0:18; and

(W=L)2 = 40=0:18. Assume nCox = 100 A/V2 and VTH = 0:4 V.

(a)If we require a bias current of 1 mA and RD = 500 , what is the highest allowable value of Vb1?

(b)With such a value chosen for Vb1, what is the value of VX ?

16.Compute the output resistance of the circuits depicted in Fig. 9.50. Assume all of the transistors operate in saturation and gmrO 1.

17.The PMOS cascode of Fig. 9.51 must provide a bias current of 0.5 mA with an output impedance of 40 k . If pCox = 50 A/V2 and = 0:2 V,1, determine the required value of (W=L)1 = (W=L)2.

VDD

R D

V1

Vb1 M 1

X

Vb2 M 2

Figure 9.49

Figure 9.50

VDD

Vb2 M 2

Vb1 M 1

R out

Figure 9.51

18.The PMOS cascode of Fig. 9.51 is designed for a given output impedance, Rout. Using Eq. (9.23), explain what happens if the widths of both transistors are increased by a factor of N while the transistor lengths and bias currents remain unchanged. Assume / L,1.

19.Determine the output impedance of the stages shown in Fig. 9.52. Assume all of the transistors operate in saturation and gmrO 1.

20.Compute the short-circuit transconductance and the voltage gain of each of the stages in Fig. 9.53. Assume > 0 and VA < 1.

21.Prove that Eq. (9.53) reduces to

V 2

Av A ; (9.130)

VT (VA + VT )

a quantity independent of the bias current.

22.The cascode stage of Fig. 9.16(b) must be designed for a voltage gain of 500. If 1 = 2 = 100, determine the minimum required value of VA1 = VA2. Assume I1 = 1 mA.

23.Having learned about the high voltage gain of the cascode stage, a student adventurously constructs the circuit depicted in Fig. 9.54, where the input is applied to the base of Q2

Figure 9.53

rather than to the base of Q1.

(a)Replacing Q1 with rO1, explain intuitively why the voltage gain of this stage cannot be as high as that of the cascode.

(b)Assuming gmrO 1, compute the short-circuit transconductance and the voltage gain.

24.Determine the short-circuit transconductance and the voltage gain of the circuit shown in Fig. 9.55.

25.Calculate the voltage gain of each stage illustrated in Fig. 9.56.

26.Consider the cascode amplifier of Fig. 9.19 and assume 1 = 2 = N , VA1 = VA2 =

VA;N , 3 = 4 = P , V31 = VA4 = VA;P . Express Eq. (9.61) in terms of these quantities. Does the result depend on the bias current?

27.Due to a manufacturing error, a bipolar cascode amplifier has been configured as shown in Fig. 9.57. Determine the voltage gain of the circuit.

28.Writing gm = p2 nCox(W=L)ID and rO = 1=( ID), express Eq. (9.72) in terms of the device parameters and plot the result as a function of ID.

29.The MOS cascode of Fig. 9.20(a) must provide a voltage gain of 200. If nCox = 100 A=V2 and = 0:1 V,1 for both transistors, determine the required value of

(W=L)1 = (W=L)2.

30.The MOS cascode of Fig. 9.20(a) is designed for a given voltage gain, Av. Using Eq. (9.79) and the result obtained in Problem 28, explain what happens if the widths of the transistors are increased by a factor of N while the transistor lengths and bias currents remain

VCC

Q 4

Vb2 Q 3

v out

Vb1Q 2

v inQ 1

Figure 9.57

unchanged.

31.Repeat Problem 30 if the lengths of both transistors are increased by a factor of N while the transistor widths and bias currents remain unchanged.

32.Due to a manufacturing error, a CMOS cascode amplifier has been configured as shown in Fig. 9.58. Calculate the voltage gain of the circuit.

VDD

Vb4 M 4

Vb3 M 3

Vout

Vb2 M 2

Vin

Vb1 M 1

Figure 9.58

35.From Eq. (9.83), determine the sensitivity of I1 to VCC, defined as @I1=@VCC. Explain intuitively why this sensitivity is proportional to the transconductance of Q1.

36.Repeat Problem 35 for Eq. (9.85) (in terms of VDD).

37.The parameters nCox and VTH in Eq. (9.85) also vary with the fabrication process. (Integrated circuits fabricated in different batches exhibit slightly different parameters.) Determine the sensitivity of I1 to VTH and explain why this issue becomes more serious at low supply voltages.

38.Having learned about the logarithmic function of the circuit in Fig. 9.23(b), a student remembers the logarithmic amplifier studied in Chapter 8 and constructs the circuit depicted in Fig. 9.60. Explain what happens.

40.Due to a manufacturing error, resistor RP has appeared in series with the emitter of Q1 in Fig. 9.62. If I1 is half of its nominal value, express the value of RP in terms of other circuit

RP

Figure 9.62

parameters. Assume QREF and Q1 are identical and 1.

41.Repeat Problem 40 for the circuit shown in Fig. 9.63, but assuming that I1 is twice its nominal value.

42.We wish to generate two currents equal to 50 A and 230 A from a reference of 130 A. Design an npn current mirror for this purpose. Neglect the base curents.

43.Repeat Example 9.15 if the reference current is equal to 180 A.

44.Due to a manufacturing error, resistor RP has appeared in series with the base of QREF in Fig. 9.64. If I1 is 10% greater than its nominal value, express the value of RP in terms of other circuit parameters. Assume QREF and Q1 are identical.

45.Repeat Problem 44 for the circuit shown in Fig. 9.65, but assuming I1 is 10% less than its nominal value.

46.Taking base currents into account, determine the value of Icopy in each circuit depicted in Fig. 9.66. Normalize the error to the nominal value of Icopy.

Figure 9.66

47.Calculate the error in Icopy for the circuits shown in Fig. 9.67.

48.Taking base currents into account, compute the error in Icopy for each of the circuits illustrated in Fig. 9.68.

49.Determine the value of RP in the circuit of Fig. 9.69 such that I1 = IREF =2. With this choice of RP , does I1 change if the threshold voltage of both transistors increases by V ?

50.Determine the value of RP in the circuit of Fig. 9.70 such that I1 = 2IREF . With this choice of RP , does I1 change if the threshold voltage of both transistors increases by V ?

51.Repeat Example 9.21 if the reference current is 0.35 mA.

52.Calculate Icopy in each of the circuits shown in Fig. 9.71. Assume all of the transistors operate in saturation.

53.Consider the MOS current mirror shown in Fig. 9.35(c) and assume M1 and M2 are identical but =6 0.

(a)How should VDS1 be chosen so that Icopy1 is exactly equal to IREF ?

(b) Determine the error in Icopy1 with respect to IREF if VDS1 is equal to VGS , VTH (so that M1 resides at the edge of saturation).

Design Problems

In the following problems, unless otherwise stated, assume IS;n = IS;p = 6 10,16 A,

VA;n = VA;p = 5 V, n = 100; p = 50; nCox = 100 A/V2, pCox = 50 A/V2,

VTH;n = 0:4 V, and VTH;p = ,0:5 V, where the subscripts n and p refer to n-type (npn or NMOS) and p-type (pnp or PMOS) devices, respectively.

54.Assuming a bias current of 1 mA, design the degenerated current source of Fig. 9.72(a) such that RE sustains a voltage approximately equal to the minimum required collector-emitter

Figure 9.72

voltage of Q2 in Fig. 9.72(b) ( 0:5 V). Compare the output impedances of the two circuits.

55.Design the cascode current source of Fig. 9.72(b) for an output impedance of 50 k . Select

Vb1 such that Q2 experiences a base-collector forward bias of only 100 mV. Assume a bias current of 1 mA.

56.We wish to design the MOS cascode of Fig. 9.73 for an output impedance of 200 k and a

R out

Vb1 M 1

Vb2 M 2

Figure 9.73

bias current of 0.5 mA.

(a)Determine (W=L)1 = (W=L)2 if = 0:1 V,1.

(b)Calculate the required value of Vb2.