Fundamentals of Microelectronics

Exercise

Repeat the above example if 6= 0.

Example 10.24

Assuming = 0, calculate the voltage gain of the topology shown in Fig. 10.36(a).

Figure 10.36 .

Solution

Grounding the midpoint of RSS and RDD, we obtain the half circuit in Fig. 10.36(b), where

RDD

Exercise

Repeat the above example if the load current sources are replaced with diode-connected PMOS devices.

10.4 Cascode Differential Amplifiers

Recall from Chapter 9 that cascode stages provide a substantially higher voltage gain than simple CE and CS stages do. Noting that the differential gain of differential pairs is equal to the single-

ended gain of their corresponding half circuits, we surmise that cascoding boosts the gain of differential pairs as well.

We begin our study with the structure depicted in Fig. 10.37(a), where Q3 and Q4 serve as cascode devices and I1 and I2 are ideal. Recognizing that the bases of Q3 and Q4 are at ac ground, we construct the half circuit shown in Fig. 10.37(b). Equation (9.51) readily gives the gain as

Figure 10.37 (a) Bipolar cascode differential pair, (b) half circuit of (a).

confirming that a differential cascode achieves a much higher gain.

The developments in Chapter 9 also suggest the use of pnp cascodes for current sources I1 and I2 in Fig. 10.37(a). Illustrated in Fig. 10.38(a), the resulting configuration can be analyzed

with the aid of its half circuit, Fig. 10.38(b). Utilizing Eq. (9.61), we express the voltage gain as

VCC

Figure 10.38 (a) Bipolar cascode differential pair with cascode loads, (b) half circuit of (a).

Called a “telescopic cascode,” the topology of Fig. 10.38(b) exemplifies the internal circuit of some operational amplifiers.

Example 10.25

Due to a manufacturing defect, a parasitic resistance has appeared between nodes A and B in the circuit of Fig. 10.39(a). Determine the voltage gain of the circuit.

Figure 10.39

Solution

The symmetry of the circuit implies that the midpoint of R1 is a virtual ground, leading to the half circuit shown in Fig. 10.39(b). Thus, R1=2 appears in parallel with rO7, lowering the output impedance of the pnp cascode. Since the value of R1 is not given, we cannot make approximations and must return to the original expression for the cascode output impedance, Eq. (9.1):

The resistance seen looking down into the npn cascode remains unchanged and approximately equal to gm3rO3(rO1jjr 2). The voltage gain is therefore equal to

Exercise

If = 50 and VA = 4 V for all transistors and IEE = 1 mA, what value of R1 degrades the gain by a factor of two?

We now turn our attention to differential MOS cascodes. Following the above developments for bipolar counterparts, we consider the simplified topology of Fig. 10.40(a) and draw the half

504 Chap. 10 Differential Amplifiers

circuit as depicted in Fig. 10.40(b). From Eq. (9.69),

Figure 10.40 (a) MOS cascode differential pair, (b) half circuit of (a).

Illustrated in Fig. 10.41(a), the complete CMOS telescopic cascode amplifier incorporates PMOS cascades as load current sources, yielding the half circuit shown in Fig. 10.41(b). It follows from Eq. (9.72) that the voltage gain is given by

Figure 10.41 (a) MOS telescopic cascode amplifier, (b) half circuit of (a).

Example 10.26

Due to a manufacturing defect, two equal parasitic resistances, R1 and R2, have appeared as shown in Fig. 10.42(a). Compute the voltage gain of the circuit.

Solution

Noting that R1 and R2 appear in parallel with rO5 and rO6, respectively, we draw the half circuit as depicted in Fig. 10.42(b). Without the value of R1 given, we must resort to the original expression for the output impedance, Eq. (9.3):

Figure 10.42

The resistance seen looking into the drain of the NMOS cascode can still be approximated as

The voltage gain is then simply equal to

Exercise

Repeat the above example if in addition to R1 and R2, a resistor of value R3 appears between the sources of M3 and M4.

10.5 Common-Mode Rejection

In our study of bipolar and MOS differential pairs, we have observed that these circuits produce no change in the output if the input CM level changes. The common-mode rejection property of differential circuits plays a critical role in today's electronic systems. As the reader may have guessed, in practice the CM rejection is not infinitely high. In this section, we examine the CM rejection in the presence of nonidealities.

The first nonideality relates to the output impedance of the tail current source. Consider the topology shown in Fig. 10.43(a), where REE denotes the output impedance of IEE. What happens if the input CM level changes by a small amount? The symmetry requires that Q1 and Q2 still carry equal currents and Vout1 = Vout2. But, since the base voltages of both Q1 and Q2 rise, so does VP . In fact, noting that Vout1 = Vout2, we can place a short circuit between the output nodes, reducing the topology to that shown in Fig. 10.43(b). That is, as far as node P is concerned, Q1 and Q2 operate as an emitter follower. As VP increases, so does the current through REE and hence the collector currents of Q1 and Q2. Consequently, the output common-mode level falls. The change in the output CM level can be computed by noting that the stage in Fig. 10.43(b) resembles a degenerated CE stage. That is, from Chapter 5,

Figure 10.43 (a) CM response of differential pair in the presence of finite tail impedance, (b) simplified circuit of (a).

where the term 2gm represents the transconductance of the parallel combination of Q1 and Q2. This quantity is called the “common-mode gain.” These observations apply to the MOS counterpart equally well. An alternative approach to arriving at (10.175) is outlined in Problem 65.

In summary, if the tail current exhibits a finite output impedance, the differential pair produces an output CM change in response to an input CM change. The reader may naturally wonder whether this is a serious issue. After all, so long as the quantity of interest is the difference between the outputs, a change in the output CM level introduces no corruption. Figure 10.44(a) illustrates such a situation. Here, two differential inputs, Vin1 and Vin2, experience some common-mode noise, Vin;CM . As a result, the base voltages of Q1 and Q2 with respect to ground appear as shown in Fig. 10.44(b). With an ideal tail current source, the input CM variation would have no effect at the output, leading to the output waveforms shown in Fig. 10.44(b). On the other hand, with REE < 1, the single-ended outputs are corrupted, but not the differential output [Fig. 10.44(c)].

In summary, the above study indicates that, in the presence of input CM noise, a finite CM gain does not corrupt the differential output and hence proves benign.4 However, if the circuit suffers from asymmetries and a finite tail current source impedance, then the differential output is corrupted. During manufacturing, random “mismatches” appear between the two sides of the differential pair; for example, the transistors or the load resistors may display slightly different dimensions. Consequently, the change in the tail current due to an input CM variation may affect the differential output.

As an example of the effect of asymmetries, we consider the simple case of load resistor mismatch. Depicted in Fig. 10.45(a) for a MOS pair,5 this imperfection leads to a difference between Vout1 and Vout2. We must compute the change in ID1 and ID2 and multiply the result by RD and RD + RD.

4Interestingly, older literature has considered this effect troublesome.

5We have chosen a MOS pair here to show that the treatment is the same for both technologies.

Figure 10.44 (a) Differential pair sensing input CM noise, (b) effect of CM noise at output with REE = 1, (c) effect of CM noise at the output with REE =61.

P

VCM

I SS RSS

Figure 10.45 MOS pair with asymmetric loads.

How do we determine the change in ID1 and ID2? Neglecting channel-length modulation, we first observe that

concluding that ID1 must be equal to ID2 because VGS1 = VGS2 and hence VGS1 =VGS2. In other words, the load resistor mismatch does not impact the symmetry of currents carried by M1 and M2.6 Writing ID1 = ID2 = ID and VGS1 = VGS2 = VGS, we recognize that both ID1 and ID2 flow through RSS, creating a voltage change of 2 IDRSS

6But with 6= 0, it would.

508 Chap. 10 Differential Amplifiers

Produced by each transistor, this current change flows through both RD and RD + RD, thereby generating a differential output change of

(This result can also be obtained through small-signal analysis.) We say the circuit exhibits “common mode to differential mode (DM) conversion” and denote the above gain by ACM,DM . In practice, we strive to minimize this corruption by maximizing the output impedance of the tail current source. For example, a bipolar current source may employ emitter degeneration and a MOS current source may incorporate a relatively long transistor. It is therefore reasonable to assume RSS 1=gm and

ACM,DM RD : (10.187)

2RSS

Example 10.27

Determine ACM,DM for the circuit shown in Fig. 10.46. Assume VA = 1 for Q1 and Q2.

Solution

Recall from Chapter 5 that emitter degeneration raises the output impedance to

Q 1 Q 2

P

VCM

R out3

VbQ 3

R1

Figure 10.46

Exercise

Calculate the above result if R1 ! 1.

The mismatches between the transistors in a differential pair also lead to CM-DM conversion. This effect is beyond the scope of this book [1].

While undesirable, CM-DM conversion cannot be simply quantified by ACM,DM . If the circuit provides a large differential gain, ADM , then the relative corruption at the output is small. We therefore define the “common-mode rejection ratio” (CMRR) as

Representing the ratio of “good” to “bad,” CMRR serves as a measure of how much wanted signal and how much unwanted corruption appear at the output if the input consists of a differential component and common-mode noise.

Example 10.28

Calculate the CMRR of the circuit in Fig. 10.46.

Solution

For small mismatches (e.g., 1%), RC RC, and the differential gain is equal to gm1RC. Thus,

Exercise

Determine the CMRR if R1 ! 1.

10.6 Differential Pair with Active Load

In this section, we study an interesting combination of differential pairs and current mirrors that proves useful in many applications. To arrive at the circuit, let us first address a problem encountered in some cases.

Recall that the op amps used in Chapter 8 have a differential input but a single-ended output [Fig. 10.47(a)]. Thus, the internal circuits of such op amps must incorporate a stage that “converts” a differential input to a single-ended output. We may naturally consider the topology shown in Fig. 10.47(b) as a candidate for this task. Here, the output is sensed at node Y with respect to ground rather than with respect to node X.7 Unfortunately, the voltage gain is now halved because the signal swing at node X is not used.

Figure 10.47 (a) Circuit with differential input and single-ended output, (b) possible implementation of

(a).

We now introduce a topology that serves the task of “differential to single-ended” conversion while resolving the above issues. Shown in Fig. 10.48, the circuit employs a symmetric differential pair, Q1-Q2, along with a current-mirror load, Q3-Q4. (Transistors Q3 and Q4 are also identical.) The output is sensed with respect to ground.

I EE

Figure 10.48 Differential pair with active load.

7In practice, additional stages precede this stage so as to provide a high gain.