Fundamentals of Microelectronics

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Figure 10.26 Response of MOS pair to small differential inputs.

Example 10.16

Design an NMOS differential pair for a voltage gain of 5 and a power budget of 2 mW subject to the condition that the stage following the differential pair requires an input CM level of at least 1.6 V. Assume nCox = 100 A=V2, = 0, and VDD = 1:8 V.

Solution

For VCM;out = 1:6 V, each resistor must sustain a voltage drop of no more than 200 mV, thereby assuming a maximum value of

Setting gmRD = 5, we must choose the transistor dimensions such that gm = 5=(360 ). Since each transistor carries a drain current of ISS=2,

The large aspect ratio arises from the small drop allowed across the load resistors.

Exercise

If the aspect ratio must remain below 200, what voltage gain can be achieved?

Example 10.17

What is the maximum allowable input CM level in the above example if VTH = 0:4 V?

Solution

We rewrite (10.107) as

Interestingly, the input CM level can comfortably remain at VDD. In contrast to Example 10.5, the constraint on the load resistor in this case arises from the output CM level requirement.

Exercise

Does the above result hold if VTH = 0:2 V.

Example 10.18

The common-source stage and the differential pair shown in Fig. 10.28 incorporate equal load resistors. If the two circuits are designed for the same voltage gain and the same supply voltage, discuss the choice of (a) transistor dimensions for a given power budget, (b) power dissipation for given transistor dimensions.

Solution

(a) For the two circuits to consume the same amount of power ID1 = ISS = 2ID2 = 2ID3; i.e.,

each transistor in the differential pair carries a current equal to half of the drain current of the CS transistor. Equation (10.121) therefore requires that the differential pair transistors be twice as wide as the CS device to obtain the same voltage gain. (b) If the transistors in both circuits have the same dimensions, then the tail current of the differential pair must be twice the bias current of the CS stage for M1-M3 to have the same transconductance, doubling the power consumption.

Exercise

Discuss the above results if the CS stage and the differential pair incorporate equal source degeneration resistors.

10.3.2 Large-Signal Analysis

As with the large-signal analysis of the bipolar pair, our objective here is to derive the input/output characteristics of the MOS pair as the differential input varies from very negative to very positive values. From Fig. 10.29.

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Figure 10.29 MOS differential pair for large-signal analysis.

To obtain ID1 , ID2, we neglect channel-length modulation and write a KVL around the input network and a KCL at the tail node:

The symmetry of the circuit also implies that

Equations (10.140)-(10.142) form the foundation of our understanding of the MOS differential pair.

Let us now examine (10.142) closely. As expected from the characteristics in Fig. 10.25(c), the right-hand side is an odd (symmetric) function of Vin1 , Vin2, dropping to zero for a zero input difference. But, can the difference under the square root vanish, too? That would suggest that ID1 , ID2 falls to zero as (Vin1 , Vin2)2 reaches 4ISS=( nCoxW=L) , an effect not predicted by our qualitative sketches in Fig. 10.25(c). Furthermore, it appears that the argument of the square root becomes negative as (Vin1 , Vin2)2 exceeds this value! How should these results be interpreted?

Implicit in our foregoing derivations is the assumption that both transistors are on. However, as jVin1 , Vin2j rises, at some point that M1 or M2 turns off, violating the above equations. We must therefore determine the input difference that places one of the transistors at the edge of conduction. This can be accomplished by equating (10.140), (10.141), or (10.142) to ISS, but leading to lengthy algebra. Instead, we recognize from Fig. 10.30 that if, for example, M1

Figure 10.30 MOS differential pair with one device off.

approaches the edge of conduction, then its gate-source voltage falls to a value equal to VTH. Also, the gate-source voltage of M2 must be sufficiently large to accommodate a drain current of

ISS:

t nCox L

where jVin1 , Vin2jmax denotes the input difference that places one transistor at the edge of conduction. Equation (10.145) is invalid for input differences greater than this value. Indeed,

substituting from (10.145) in (10.142) also yields jID1 , ID2j = ISS. We also note that jVin1 , Vin2jmax can be related to the equilibrium overdrive [Eq. (10.106)] as follows:

The above findings are very important and stand in contrast to the behavior of the bipolar differential pair and Eq. (10.78): the MOS pair steers all of the tail current3 for jVin1 ,Vin2jmax whereas the bipolar counterpart only approaches this condition for a finite input difference. Equation (10.146) provides a great deal of intuition into the operation of the MOS pair. Specifically, we plot ID1 and ID2 as in Fig. 10.31(a), where Vin = Vin1 , Vin2, arriving at the differential characteristics in Figs. 10.31(b) and (c). The circuit thus behaves linearly for small values of Vin and becomes completely nonlinear for Vin > Vin;max. In other words, Vin;max serves as an absolute bound on the input signal levels that have any effect on the output.