Fundamentals of Microelectronics

Figure 10.13 Variation of currents and voltages as a function of input.

Figure 10.14

differential input is equal to 2 mV. The outputs are therefore sinusoids having a peak amplitude of 1 mV gmRC [Fig. 10.14(d)]. On the other hand, the sinusoids in Fig. 10.14(c) force a maximum input difference of 200 mV, turning Q1 or Q2 off. For example, as Vin1 approaches 50 mV above VCM and Vin2 reaches 50 mV below VCM (at t = t1), Q1 absorbs most of the tail current, thus producing

Thereafter, the outputs remain saturated until jVin1 , Vin2j falls to less than 100 mV. The result is sketched in Fig. 10.14(e). We say the circuit operates as a “limiter” in this case, playing a role similar to the diode limiters studied in Chapter 3.

Exercise

What happens to the above results if the tail current is halved?

10.2.3 Small-Signal Analysis

Our brief investigation of the differential pair in Fig. 10.11 revealed that, for small differential inputs, the tail node maintains a constant voltage (and hence is called a “virtual ground”). We also obtained a voltage gain equal to gmRC. We now study the small-signal behavior of the circuit in greater detail. As explained in previous chapters, the definition of “small signals” is somewhat arbitrary, but the requirement is that the input signals not influence the bias currents of Q1 and Q2 appreciably. In other words, the two transistors must exhibit approximately equal transconductances—the same condition required for node P to appear as virtual ground. In practice, an input difference of less than 10 mV is considered “small” for most applications.

Assuming perfect symmetry, an ideal tail current source, and VA = 1, we construct the small-signal model of the circuit as shown in Fig. 10.15(a). Here, vin1 and vin2 represent small changes in each input and must satisfy vin1 = ,vin2 for differential operation. Note that the tail current source is replaced with an open circuit. As with the foregoing large-signal analysis, let us write a KVL around the input network and a KCL at node P :

Thus, the small-signal model confirms the prediction made by (10.32). In Problem 28, we prove that this property holds in the presence of Early effect as well.

The virtual-ground nature of node P for differential small-signal inputs simplifies the analysis considerably. Since vP = 0, this node can be shorted to ac ground, reducing the differential pair of Fig. 10.15(a) to two “half circuits” [Fig. 10.15(b)]. With each half resembling a commonemitter stage, we can write

(c)

Figure 10.15 (a) Small-signal model of bipolar pair, (b) simplified small-signal model, (c) simplied diagram.

It follows that the differential voltage gain of the differential pair is equal to

the same as that expressed by (10.40). For simplicity, we may draw the two half circuits as in Fig. 10.15(c), with the understanding that the incremental inputs are small and differential. Also, since the two halves are identical, we may draw only one half.

Example 10.10

Compute the differential gain of the circuit shown in Fig. 10.16(a), where ideal current sources are used as loads to maximize the gain.

Solution

With ideal current sources, the Early effect in Q1 and Q2 cannot be neglected, and the half circuits must be visualized as depicted in Fig. 10.16(b). Thus,

Exercise

Calculate the gain for VA = 5 V.

Example 10.11

Figure 10.17(a) illustrates an implementation of the topology shown in Fig. 10.16(a). Calculate the differential voltage gain.

Figure 10.17

Solution

Noting that each pnp device introduces a resistance of rOP at the output nodes and drawing the half circuit as in Fig. 10.17(b), we have

where rON denotes the output impedance of the npn transistors.

Exercise

Calculate the gain if Q3 and Q4 are configured as diode-connected devices.

We must emphasize that the differential voltage gain is defined as the difference between the outputs divided by the difference between the inputs. As such, this gain is equal to the singleended gain of each half circuit.

We now make an observation that proves useful in the analysis of differential circuits. As noted above, the symmetry of the circuit (gm1 = gm2) establishes a virtual ground at node P in Fig. 10.12 if the incremental inputs are small and differential. This property holds for any other node that appears on the axis of symmetry. For example, the two resistors shown in Fig. 10.18 create a virtual ground at X if (1) R1 = R2 and (2) nodes A and B vary by equal and opposite amounts.2 Additional examples make this concept clearer. We assume perfect symmetry in each case.

Figure 10.18

Example 10.12

Determine the differential gain of the circuit in Fig. 10.19(a) if VA < 1.

Figure 10.19

Solution

Drawing one of the half circuits as shown in Fig. 10.19(b), we express the total resistance seen at the collector of Q1 as

2Since the resistors are linear, the signals need not be small in this case.

Exercise

Repeat the above example if R1 =6 R2.

Example 10.13

Calculate the differential gain of the circuit illustrated in Fig. 10.20(a) if VA < 1.

Figure 10.20

Solution

For small differential inputs and outputs, VX remains constant, leading to the conceptual half circuit shown in Fig. 10.20(b)—the same as that in the above example. This is because Q3 and Q4 experience a constant base-emitter voltage in both cases, thereby serving as current sources and exhibiting only an output resistance. It follows that

Exercise

Calculate the gain if VA = 4 V for all transistors, R1 = R2 = 10 k , and IEE = 1 mA.

Example 10.14

Determine the gain of the degenerated differential pairs shown in Figs. 10.21(a) and (b). Assume

VA = 1.

Solution

In the topology of Fig. 10.21(a), node P is a virtual ground, yielding the half circuit depicted in

Figure 10.21

In the circuit of Fig. 10.21(b), the line of symmetry passes through the “midpoint” of RE. In other words, if RE is regarded as two RE =2 units in series, then the node between the units acts as a virtual ground [Fig. 10.21(d)]. It follows that

The two circuits provide equal gains if the pair in Fig. 10.21(b) incorporates a total degeneration resistance of 2RE.

Exercise

Design each circuit for a gain of 5 and power consumption of 2 mW. Assume VCC = 2:5 V, VA = 1, and RE = 2=gm.

I/O Impedances For a differential pair, we can define the input impedance as illustrated in Fig. 10.22(a). From the equivalent circuit in Fig. 10.22(b), we have

Figure 10.22 (a) Method for calculation of differential input impedance, (b) equivalent circuit of (a).

as if the two base-emitter junctions appear in series.

The above quantity is called the “differential input impedance” of the circuit. It is also possible to define a “single-ended input impedance” with the aid of a half circuit (Fig. 10.23), obtaining

VCC

RC

i X

Q 1

v X

Figure 10.23 Calculation of single-ended input impedance.

This result provides no new information with respect to that in (10.102) but proves useful in some calculations.

In a manner similar to the foregoing development, the reader can show that the differential and single-ended output impedances are equal to 2RC and RC, respectively.

10.3 MOS Differential Pair

Most of the principles studied in the previous section for the bipolar differential pair apply directly to the MOS counterpart as well. For this reason, our treatment of the MOS circuit in this section is more concise. We continue to assume perfect symmetry.

10.3.1 Qualitative Analysis

Figure 10.24(a) depicts the MOS pair with the two inputs tied to VCM , yielding

Figure 10.24 Response of MOS differential pair to input CM variation.

That is, a zero differential input gives a zero differential output. Note that the output CM level is equal to VDD , RDISS=2.

For our subsequent derivations, it is useful to compute the “equilibrium overdrive voltage” of M1 and M2, (VGS ,VTH)equil:. We assume = 0 and hence ID = (1=2) nCox(W=L)(VGS , VTH )2. Carrying a current of ISS=2, each device exhibits an overdrive of

As expected, a greater tail current or a smaller W=L translates to a larger equilibrium overdrive. To guarantee that M1 and M2 operate in saturation, we require that their drain voltages not

fall below VCM , VTH:

It can also be observed that a change in VCM cannot alter ID1 = ID2 = ISS=2, leaving VX and VY undisturbed. The circuit thus rejects input CM variations.

Example 10.15

A MOS differential pair is driven with an input CM level of 1.6 V. If ISS = 0:5 mA, VTH = 0:5 V, and VDD = 1:8 V, what is the maximum allowable load resistance?

Solution

We may suspect that this limitation in turn constrains the voltage gain of the circuit, as explained later.

Exercise

What is the maximum tail current if the load resistance is 5 k .

Figure 10.25 illustrates the response of the MOS pair to large differential inputs. If Vin1 is well above Vin2 [Fig. 10.25(a)], then M1 carries the entire tail current, generating

(c)

Figure 10.25 (a) Response of MOS differential pair to very positive input, (b) response of MOS differential pair to very negative input, (c) qualitative plots of currents and voltages.

The circuit therefore steers the tail current from one side to the other, producing a differential output in response to a differential input. Figure 10.25(c) sketches the characteristics of the circuit.

Let us now examine the circuit's behavior for a small input difference. Depicted in Fig. 10.26(a), such a scenario maintains VP constant because Eqs. (10.27)-(10.32) apply to this case equally well. It follows that