Fundamentals of Microelectronics

10.1.3 Differential Pair

Before formally introducing the differential pair, we must recognize that the circuit of Fig. 10.4(b) senses two inputs and can therefore serve as A1 in Fig. 10.2(b). This observation leads to the differential pair.

While sensing and producing differential signals, the circuit of Fig. 10.4(b) suffers from some drawbacks. Fortunately, a simple modification yields an elegant, versatile topology. Illustrated in Fig. 10.6(a), the (bipolar) “differential pair” 1 is similar to the circuit of Fig. 10.4(b), except that the emitters of Q1 and Q2 are tied to a constant current source rather than to ground. We call IEE the “tail current source.” The MOS counterpart is shown in Fig. 10.6(b). In both cases, the sum of the transistor currents is equal to the tail current. Our objective is to analyze the large-signal and small-signal behavior of these circuits and demonstrate their advantages over the “single-ended” stages studied in previous chapters.

Figure 10.6 (a) Bipolar and (b) MOS differential pairs.

For each differential pair, we begin with a qualitative, intuitive analysis and subsequently formulate the large-signal and small-signal behavior. We also assume each circuit is perfectly symmetric, i.e., the transistors are identical and so are the resistors.

10.2 Bipolar Differential Pair

10.2.1 Qualitative Analysis

It is instructive to first examine the bias conditions of the circuit. Recall from Section 10.1.2 that in the absence of signals, differential nodes reside at the common-mode level. We therefore draw the pair as shown in Fig. 10.7, with the two inputs tied to VCM to indicate no signal exists at the input. By virtue of symmetry,

where the collector and emitter currents are assumed equal. We say the circuit is in “equilibrium.” Thus, the voltage drop across each load resistor is equal to RCIEE=2 and hence

1Also called the “emitter-coupled pair” or the “long-tailed pair.”

Figure 10.7 Response of differential pair to input CM change.

In other words, if the two input voltages are equal, so are the two outputs. We say a zero differential input produces a zero differential output. The circuit also “rejects” the effect of supply ripple: if VCC experiences a change, the differential output, VX , VY , does not.

Are Q1 and Q2 in the active region? To avoid saturation, the collector voltages must not fall below the base voltages:

revealing that VCM cannot be arbitrarily high.

Example 10.4

A bipolar differential pair employs a load resistance of 1 k and a tail current of 1 mA. How close to VCC can VCM be chosen?

Solution

That is, VCM must remain below VCC by at least 0.5 V.

Exercise

What value of RC allows the input CM level to approach VCC is the transistors can tolerate a base-collector forward bias of 400 mV?

Now, let us vary VCM in Fig. 10.7 by a small amount and determine the circuit's response. Interestingly, Eqs. (10.13)-(10.15) remain unchanged, thereby suggesting that neither the collector current nor the collector voltage of the transistors is affected. We say the circuit does not respond to changes in the input common-mode level; or the circuit “rejects” input CM variations. Figure 10.8 summarizes these results.

The “common-mode rejection” capability of the differential pair distinctly sets it apart from our original circuit in Fig. 10.4(b). In the latter, if the base voltage of Q1 and Q2 changes, so do their collector currents and voltages (why?). The reader may recognize that it is the tail current source in the differential pair that guarantees constant collector currents and hence rejection of the input CM level.

With our treatment of the common-mode response, we now turn to the more interesting case of differential response. We hold one input constant, vary the other, and examine the currents flowing in the two transistors. While not exactly differential, such input signals provide a simple, intuitive starting point. Recall that IC1 + IC2 = IEE.

Consider the circuit shown in Fig. 10.9(a), where the two transistors are drawn with a vertical offset to emphasize that Q1 senses a more positive base voltage. Since the difference between the base voltages of Q1 and Q2 is so large, we postulate that Q1 “hogs” all of the tail current, thereby turning Q2 off. That is,

Figure 10.9 Response of bipolar differential pair to (a) large positive input difference and (b) large negative input difference.

But, how can we prove that Q1 indeed absorbs all of IEE? Let us assume that it is not so; i.e., IC1 < IEE and IC2 =6 0. If Q2 carries an appreciable current, then its base-emitter voltage must reach a typical value of, say, 0.8 V. With its base held at +1 V, the device therefore requires an emitter voltage of VP 0:2 V. However, this means that Q1 sustains a base-emitter voltage of Vin1 , VP = +2 V , 0:2 V = 1:8 V!! Since with VBE = 1:8 V, a typical transistor carries an enormous current, and since IC1 cannot exceed IEE, we conclude that the conditions VBE1 = 1:8 V and VP 0:2 V cannot occur. In fact, with a typical base-emitter voltage of 0.8 V, Q1 holds node P at approximately +1:2 V, ensuring that Q2 remains off.

Symmetry of the circuit implies that swapping the base voltages of Q1 and Q2 reverses the situation [Fig. 10.9(b)], giving

The above experiments reveal that, as the difference between the two inputs departs from zero, the differential pair “steers” the tail current from one transistor to the other. In fact, based on Eqs. (10.14), (10.19), and (10.23), we can sketch the collector currents of Q1 and Q2 as a function of the input difference [Fig. 10.10(a)]. We have not yet formulated these characteristics but we do observe that the collector current of each transistor goes from 0 to IEE if jVin1 , Vin2j becomes sufficiently large.

Figure 10.10 Variation of (a) collector currents and (b) output voltages as a function of input.

It is also important to note that VX and VY vary differentially in response to Vin1 ,Vin2. From Eqs. (10.15), (10.21), and (10.25), we can sketch the input/output characteristics of the circuit as shown in Fig. 10.10(b). That is, a nonzero differential input yields a nonzero differential output— a behavior in sharp contrast to the CM response. Since VX and VY are differential, we can define a common-mode level for them. Given by VCC , RCIEE=2, this quantity is called the “output CM level.”

Example 10.5

A bipolar differential pair employs a tail current of 0.5 mA and a collector resistance of 1 k . What is the maximum allowable base voltage if the differential input is large enough to completely steer the tail current? Assume VCC = 2:5 V.

Solution

If IEE is completely steered, the transistor carrying the current lowers its collector voltage to VCC , RC IEE = 2 V. Thus, the base voltage must remain below this value so as to avoid saturation.

Exercise

Repeat the above example if the tail current is raised to 1 mA.

In the last step of our qualitative analysis, we “zoom in” around Vin1 ,Vin2 = 0 (the equilibrium condition) and study the circuit's behavior for a small input difference. As illustrated in Fig. 10.11(a), the base voltage of Q1 is raised from VCM by V while that of Q2 is lowered from VCM by the same amount. We surmise that IC1 increases slightly and, since IC1 + IC2 = IEE, IC2 decreases by the same amount:

Figure 10.11 (a) Differential pair sensing small, differential input changes, (b) hypothetical change at P.

How is I related to V ? If the emitters of Q1 and Q2 were directly tied to ground, then I would simply be equal to gm V . In the differential pair, however, node P is free to rise or fall. We must therefore compute the change in VP .

Suppose, as shown in Fig. 10.11(b), VP rises by VP . As a result, the net increase in VBE1 is equal to V , VP and hence

Interestingly, the tail voltage remains constant if the two inputs vary differentially and by a small amount—an observation critical to the small-signal analysis of the circuit.

The reader may wonder why (10.32) does not hold if V is large. Which one of the above equations is violated? For a large differential input, Q1 and Q2 carry significantly different currents, thus exhibiting unequal transconductances and prohibiting the omission of gm's from the two sides of (10.31).

With VP = 0 in Fig. 10.11(a), we can rewrite (10.29) and (10.30) respectively as

(Note that the change in the differential input is equal to 2 V .) This expression is similar to that of the common-emitter stage.

Example 10.6

Design a bipolar differential pair for a gain of 10 and a power budget of 1 mW with a supply voltage of 2 V.

Solution

With VCC = 2 V, the power budget translates to a tail current of 0.5 mA. Each transistor thus carries a current of 0.25 mA near equilibrium, providing a transconductance of 0:25 mA=26 mV = (104 ),1. It follows that

Exercise

Redesign the circuit for a power budget of 0.5 mW and compare the results.

Sec. 10.2 Bipolar Differential Pair 477

Example 10.7

Compare the power dissipation of a bipolar differential pair with that of a CE stage if both circuits are designed for equal voltage gains, collector resistances, and supply voltages.

Solution

where IEE=2 is the bias current of each transistor in the differential pair, and IC represents the bias current of the CE stage. In other words,

indicating that the differential pair consumes twice as much power. This is one of the drawbacks of differential circuits.

Exercise

If both circuits are designed for the same power budget, equal collector resistances, and equal supply voltages, compare their voltage gains.

10.2.2 Large-Signal Analysis

Having obtained insight into the operation of the bipolar differential pair, we now quantify its large-signal behavior, aiming to formulate the input/output characteristic of the circuit (the sketches in Fig. 10.10). Not having seen any large-signal analysis in the previous chapters, the reader may naturally wonder why we are suddenly interested in this aspect of the differential pair. Our interest arises from (a) the need to understand the circuit's limitations in serving as a linear amplifier, and (b) the application of the differential pair as a (nonlinear) current-steering circuit.

In order to derive the relationship between the differential input and output of the circuit, we first note from Fig. 10.12 that

P

I EE

Figure 10.12 Bipolar differential pair for large-signal analysis.

and hence

We must therefore compute IC1 and IC2 in terms of the input difference. Assuming = 1 and VA = 1, and recalling from Chapter 4 that VBE = VT ln(IC=IS), we write a KVL around the input network,

Equations (10.55) and (10.56) contain two unknowns. Substituting for IC1 from (10.55) in (10.56) yields

The symmetry of the circuit with respect to Vin1 and Vin2 and with respect to IC1 and IC2 suggests that IC1 exhibits the same behavior as (10.58) but with the roles of Vin1 and Vin2

Sec. 10.2 Bipolar Differential Pair 479

exchanged:

Alternatively, the reader can substitute for IC2 from (10.58) in (10.56) to obtain IC1.

Equations (10.58) and (10.60) play a crucial role in our quantitative understanding of the differential pair's operation. In particular, if Vin1 , Vin2 is very negative, then exp(Vin1 ,

as predicted by our qualitative analysis [Fig. 10.9(b)]. Similarly, if Vin1 , Vin2 is very positive, exp(Vin1 , Vin2)=VT ! 1 and

In other words, Q1 carries only 0:0045% of the tail current; and IEE can be considered steered completely to Q2.

Example 10.8

Determine the differential input voltage that steers 98% of the tail current to one transistor.

Solution

We require that

We often say a differential input of 4VT is sufficient to turn one side of the bipolar pair nearly off. Note that this value remains independent of IEE and IS.

Figure 10.13 summarizes the results, indicating that the differential output voltage begins from a “saturated” value of +RCIEE for a very negative differential input, gradually becomes a linear function of Vin1 , Vin2 for relatively small values of jVin1 , Vin2j, and reaches a saturated level of ,RCIEE as Vin1 , Vin2 becomes very positive. From Example 10.8, we recognize that even a differential input of 4VT 104 mV “switches” the differential pair, thereby concluding that jVin1 , Vin2j must remain well below this value for linear operation.

Example 10.9

Sketch the output waveforms of the bipolar differential pair in Fig. 10.14(a) in response to the sinusoidal inputs shown in Figs. 10.14(b) and (c). Assume Q1 and Q2 remain in the forward active region.

Solution

For the sinusoids depicted in Fig. 10.14(b), the circuit operates linearly because the maximum