Fundamentals of Microelectronics

accomplished as depicted in Fig. 8.22(b), where D1 is inserted in the feedback loop. Note that Vout is sensed at X rather than at the output of the op amp.

Vout

t

Figure 8.22 (a) Simple op amp circuit, (b) precision rectifier, (c) circuit waveforms.

To analyze the operation of this circuit, let us first assume that Vin = 0. In its attempt to minimize the voltage difference between the noninverting and the inverting inputs, the op amp raises VY to approximately VD1;on, turning D1 barely on but with little current so that VX 0. Now if Vin becomes slightly positive, VY rises further so that the current flowing through D1 and R1 yields Vout Vin. That is, even small positive levels at the input appear at the output.

What happens if Vin becomes slightly negative? For Vout to assume a negative value, D1 must carry a current from X to Y , which is not possible. Thus, D1 turns off and the op amp produces a very large negative output (near the negative supply rail) because its noninverting input falls below its inverting input. Figure 8.22(c) plots the circuit's waveforms in response to an input sinusoid.

Example 8.9

Plot the waveforms in the circuit of Fig. 8.23(a) in response to an input sinusoid.

Vin

Figure 8.23 (a) Inverting precision rectifier, (b) circuit waveforms.

Solution

For Vin = 0, the op amp creates VY ,VD;on so that D1 is barely on, R1 carries little current, and X is a virtual ground. As Vin becomes positive, thus raising the current through R1, VY only slightly decreases to allow D1 to carry the higher current. That is, VX 0 and VY ,VD;on for positive input cycles.

For Vin < 0, D1 turns off (why?), leading to VX = Vin and driving VY to a very positive value. Figure 8.23(b) shows the resulting waveforms.

Exercise

Repeat the above example for a triangular input that goes from ,2 V to +2 V.

The large swings at the output of the op amp in Figs. 8.22(b) and 8.23(a) lower the speed of the circuit as the op amp must “recover” from a saturated value before it can turn D1 on again. Additional techniques can resolve this issue (Problem 39).

8.3.2 Logarithmic Amplifier

Consider the circuit of Fig. 8.24, where a bipolar transistor is placed around the op amp. With an ideal op amp, R1 carries a current equal to Vin=R1 and so does Q1. Thus,

Vin

R 1

Q 1

R1 X

Vout

Vin

Figure 8.24 Logarithmic amplifier.

The output is therefore proportional to the natural logarithm of Vin. As with previous linear and nonlinear circuits, the virtual ground plays an essential role here as it guarantees the current flowing through Q1 is xactly proportional to Vin.

Logarithmic amplifiers (“logamps”) prove useful in applications where the input signal level may vary by a large factor. It may be desirable in such cases to amplify weak signals and attenuate (“compress”) strong signals; hence a logarithmic dependence.

The negative sign in (8.66) is to be expected: if Vin rises, so do the currents flowing through R1 and Q1, requiring an increase in VBE. Since the base is at zero, the emitter voltage must fall below zero to provide a greater collector current. Note that Q1 operates in the active region because both the base and the collector remain at zero. The effect of finite op amp gain is studied in Problem 41.

The reader may wonder what happens if Vin becomes negative. Equation (8.66) predicts that Vout is not defined. In the actual circuit, Q1 cannot carry a “negative” current, the loop around the op amp is broken, and Vout approaches the negative supply rail. It is therefore necessary to ensure Vin remains positive.

8.3.3 Square-Root Amplifier

Recognizing that the logarithmic amplifier of Fig. 8.24 in fact implements the inverse function of the exponential characteristic, we surmise that replacing the bipolar transistor with a MOSFET

t nCox L R1

If Vin is near zero, then Vout remains at ,VTH, placing M1 at the edge of conduction. As Vin becomes more positive, Vout falls to allow M1 to carry a greater current. With its gate and drain at zero, M1 operates in saturation.

8.4 Op Amp Nonidealities

Our study in previous sections has dealt with a relatively idealized op amp model—except for the finite gain—so as to establish insight. In practice, however, op amps suffer from other imperfections that may affect the performance significantly. In this section, we deal with such nonidealities.

8.4.1 DC Offsets

The op amp characteristics shown in Fig. 8.2 imply that Vout = 0 if Vin1 = Vin2. In reality, a zero input difference may not give a zero output difference! Illustrated in Fig. 8.26(a), the

Figure 8.26 (a) Offset in an op amp, (b) mismatch between input devices, (c) representation of offset.

What causes offset? The internal circuit of the op amp experiences random asymmetries (“mismatches”) during fabrication and packaging. For example, as conceptually shown in Fig.

8.26(b), the bipolar transistors sensing the two inputs may display slightly different base-emitter voltages. The same effect occurs for MOSFETs. We model the offset by a single voltage source placed in series with one of the inputs [Fig. 8.26(c)]. Since offsets are random and hence can be positive or negative, Vos can appear at either input with arbitrary polarity.

Why are DC offsets important? Let us reexamine some of the circuit topologies studied in Section 8.2 in the presence of op amp offsets. Depicted in Fig. 8.27, the noninverting amplifier now sees a total input of Vin + Vos, thereby generating

R1

R2

Figure 8.27 Offset in noninverting amplifier.

In other words, the circuit amplifies the offset as well as the signal, thus incurring accuracy limitations.6

Example 8.10

A truck weighing station employs an electronic pressure meter whose output is amplified by the circuit of Fig. 8.27. If the pressure meter generates 20 mV for every 100 kg of load and if the op amp offset is 2 mV, what is the accuracy of the weighing station?

Solution

An offset of 2 mV corresponds to a load of 10 kg. We therefore say the station has an error of10 kg in its measurements.

Exercise

What offset voltage is required for an accuracy of 1 kg?

DC offsets may also cause “saturation” in amplifiers. The following example illustrates this point.

Example 8.11

An electrical engineering student constructs the circuit shown in Fig. 8.28 to amplify the signal produced by a microphone. The targeted gain is 104 so that very low level sounds (i.e., microvolt signals) can be detected. Explain what happens if op amp A1 exhibits an offset of 2 mV.

Solution

From Fig. 8.27, we recognize that the first stage amplifies the offset by a factor of 100, generating a dc level of 200 mV at node X (if the microphone produces a zero dc output). The second stage

6The reader can show that placing Vos in series with the inverting input of the op amp yields the same result.

Figure 8.28 Two-stage amplifier.

now amplifies VX by another factor of 100, thereby attempting to generate Vout = 20 V. If A2 operates with a supply voltage of, say, 3 V, the output cannot exceed this value, the second op amp drives its transistors into saturation (for bipolar devices) or triode region (for MOSFETs), and its gain falls to a small value. We say the second stage is saturated. (The problem of offset amplification in cascaded stages can be resolved through ac coupling.)

Exercise

Repeat the above example if the second stage has a voltage gain of 10.

DC offsets impact the inverting amplifier of Fig. 8.7(a) in a similar manner. This is studied in Problem 49.

We now examine the effect of offset on the integrator of Fig. 8.10. Suppose the input is set to zero and Vos is referred to the noninverting input [Fig. 8.29(a)]. What happens at the output? Recall from Fig. 8.20 and Eq. (8.61) that the response to this “input” consists of the input itself [the unity term in (8.61)] and the integral of the input [the second term in (8.61)]. We can therefore express Vout in the time domain as

where the initial condition across C1 is assumed zero. In other words, the circuit integrates the op amp offset, generating an output that tends to +1 or ,1 depending on the sign of Vos. Of course, as Vout approaches the positive or negative supply voltages, the transistors in the op amp fail to provide gain and the output saturates [Fig. 8.29(b)].

The problem of offsets proves quite serious in integrators. Even in the presence of an input signal, the circuit of Fig. 8.29(a) integrates the offset and reaches saturation. Figure 8.29(c) depicts a modification, where resistor R2 is placed in parallel with C1. Now the effect of Vos at the output is given by (8.9) because the circuits of Figs. 8.5 and 8.29(c) are similar at low frequencies:

For example, if Vos = 2 mV and R2=R1 = 100, then Vout contains a dc error of 202 mV, but at least remains away from saturation..

Figure 8.29 (a) Offset in integrator, (b) output waveform, (c) addition of R2 to reduce effect of offset, (d) determination of transfer function.

How does R2 affect the integration function? Disregarding Vos, viewing the circuit as shown in Fig. 8.29(d), and using (8.27), we have

Thus, the circuit now contains a pole at ,1=(R2C1) rather than at the origin. If the input signal frequencies of interest lie well above this value, then R2C1s 1 and

That is, the integration function holds for input frequencies much higher than 1=(R2C1). Thus, R2=R1 must be sufficiently small so as to minimize the amplified offset given by (8.72) whereas R2C1 must be sufficiently large so as to negligibly impact the signal frequencies of interest.

8.4.2 Input Bias Current

Op amps implemented in bipolar technology draw a base current from each input. While relatively small ( 0:1-1 A), the input bias currents may create inaccuracies in some circuits. As shown in Fig. 8.30, each bias current is modeled by a current source tied between the corresponding input and ground. Nominally, IB1 = IB2.

Let us study the effect of the input currents on the noninverting amplifier. As depicted in Fig. 8.31(a), IB1 has no effect on the circuit because it flows through a voltage source. The current IB2, on the other hand, flows through R1 and R2, introducing an error. Using superposition and setting Vin to zero, we arrive at the circuit in Fig. 8.31(b), which can be transformed to that in Fig. 8.31(c) if IB2 and R2 are replaced with their Thevenin equivalent. Interestingly, the circuit now resembles the inverting amplifier of Fig. 8.7(a), thereby yielding

Figure 8.30 Input bias currents.

Vout

R1

R2

− I B2 R2

(c)

Figure 8.31 (a) Effect of input bias currents on noninverting amplifier, (b) simplified circuit, (c) Thevenin equivalent.

if the op amp gain is infinite. This expression suggests that IB2 flows only through R1, an expected result because the virtual ground at X in Fig. 8.31(b) forces a zero voltage across R2 and hence a zero current through it.

The error due to the input bias current appears similar to the DC offset effects illustrated in Fig. 8.27, corrupting the output. However, unlike DC offsets, this phenomenon is not random; for a given bias current in the bipolar transistors used in the op amp, the base currents drawn from the inverting and noninverting inputs remain approximately equal. We may therefore seek a method of canceling this error. For example, we can insert a corrective voltage in series with the noninverting input so as to drive Vout to zero (Fig. 8.32). Since Vcorr “sees” a noninverting amplifier, we have

Figure 8.32 Addition of voltage source to correct for input bias currents.

Example 8.12

A bipolar op amp employs a collector current of 1 mA in each of the input devices. If = 100 and the circuit of Fig. 8.32 incorporates R2 = 1 k , R1 = 10 k , determine the output error and the required value of Vcorr.

Solution

Exercise

Determine the correction voltage if = 200.

Equation (8.78) implies that Vcorr depends on IB2 and hence the current gain of transistors. Since varies with process and temperature, Vcorr cannot remain at a fixed value and must “track” . Fortunately, (8.78) also reveals that Vcorr can be obtained by passing a base current through a resistor equal to R1jjR2, leading to the topology shown in Fig. 8.33. Here, if IB1 = IB2, then Vout = 0 for Vin = 0. The reader is encouraged to take the finite gain of the op amp into account and prove that Vout is still near zero.

Figure 8.33 Correction for variation of beta.

From the drawing in Fig. 8.31(b), we observe that the input bias currents have an identical effect on the inverting amplifier. Thus, the correction technique shown in Fig. 8.33 applies to this circuit as well.

In reality, asymmetries in the op amp's internal circuitry introduce a slight (random) mismatch between IB1 and IB2. Problem 53 studies the effect of this mismatch on the output in Fig. 8.33.

We now consider the effect of the input bias currents on the performance of integrators. Illustrated in Fig. 8.34(a) with Vin = 0 and IB1 omitted (why?), the circuit forces IB2 to flow through C1 because R1 sustains a zero voltage drop. In fact, the Thevenin equivalent of R1 and

Figure 8.34 (a) Effect of input bias currents on integrator, (b) Thevenin equivalent.

(Of course, the flow of IB2 through C1 leads to the same result.) In other words, the circuit integrates the input bias current, thereby forcing Vout to eventually saturate near the positive or negative supply rails.

Can we apply the correction technique of Fig. 8.33 to the integrator? The model in Fig. 8.34(b) suggests that a resistor equal to R1 placed in series with the noninverting input can cancel the effect. The result is depicted in Fig. 8.35.

C1

R1

R 1

Figure 8.35 Correction for input currents in an integrator.

Example 8.13

An electrical engineering student attempts the topology of Fig. 8.35 in the laboratory but observes that the output still saturates. Give three possible reasons for this effect.

Solution

First, the DC offset voltage of the op amp itself is still integrated (Section 8.4.1). Second, the two input bias currents always suffer from a slight mismatch, thus causing incomplete cancellation. Third, the two resistors in Fig. 8.35 also exhibit mismatches, creating an additional error.

Exercise

Is resistor R1 necessary if the internal circuitry of the op amp uses MOS devices?

The problem of input bias current mismatch requires a modification similar to that in Fig. 8.29(c). The mismatch current then flows through R2 rather than through C1 (why?).

8.4.3 Speed Limitations

Finite Bandwidth Our study of op amps has thus far assumed no speed limitations. In reality, the internal capacitances of the op amp degrade the performance at high frequencies. For example, as illustrated in Fig. 8.36, the gain begins to fall as the frequency of operation exceeds f1. In this chapter, we provide a simple analysis of such effects, deferring a more detailed study to Chapter 11.

Av

A 0

Figure 8.36 Frequency response of an op amp.

To represent the gain roll-off shown in Fig. 8.36, we must modify the op amp model offered in Fig. 8.1. As a simple approximation, the internal circuitry of the op amp can be modeled by a first-order (one-pole) system having the following transfer function:

where !1 = 2 f1. Note that at frequencies well below !1, s=!1 1 and the gain is equal to A0. At very high frequencies, s=!1 1, and the gain of the op amp falls to unity at !u = A0!1. This frequency is called the “unity-gain bandwidth” of the op amp. Using this model, we can reexamine the performance of the circuits studied in the previous sections.

Consider the noninverting amplifier of Fig. 8.5. We utilize Eq. (8.11) but replace A0 with the above transfer function:

Multiplying the numerator and the denominator by (1 + s=!1) gives