Fundamentals of Microelectronics

Sec. 10.6 Differential Pair with Active Load 511

10.6.1 Qualitative Analysis

It is instructive to first decompose the circuit of Fig. 10.48 into two sections: the input differential pair and the current-mirror load. As depicted in Fig. 10.49(a) (along with a fictitious load RL), Q1 and Q2 produce equal and opposite changes in their collector currents in response to a differential

Figure 10.49 (a) Response of input pair to input change, (b) response of active load to current change.

change at the input, creating a voltage change of IRL across RL. Now consider the circuit in Fig. 10.49(b) and suppose the current drawn from Q3 increases from IEE=2 to IEE =2 + I. What happens? First, since the small-signal impedance seen at node N is approximately equal to 1=gm3, VN changes by I=gm3 (for small I). Second, by virtue of current mirror action, the collector current of Q4 also increases by I. As a result, the voltage across RL changes by

IRL.

In order to understand the detailed operation of the circuit, we apply small, differential changes at the input and follow the signals to the output (Fig. 10.50). The load resistor, RL, is added to augment our intuition but it is not necessary for the actual operation. With the input voltage changes shown here, we note that IC1 increases by some amount I and IC2 decreases by the same amount. Ignoring the role of Q3 and Q4 for the moment, we observe that the fall in IC2 translates to a rise in Vout because Q2 draws less current from RL. The output change can therefore be an amplified version of V .

VCC

P

I EE

Figure 10.50 Detailed operation of pair with active load.

Let us now determine how the change in IC1 travels through Q3 and Q4. Neglecting the base currents of these two transistors, we recognize that the change in IC3 is also equal to I. This change is copied into IC4 by virtue of the current mirror action. In other words, in response to the differential input shown in Fig. 10.50, IC1, jIC3j, and jIC4j increase by I. Since Q4 “injects” a greater current into the output node, Vout rises.

In summary, the circuit of Fig. 10.50 contains two signal paths, one through Q1 and Q2 and another through Q1, Q3 and Q4 [Fig. 10.51(a)]. For a differential input change, each path experiences a current change, which translates to a voltage change at the output node. The key point here is that the two paths enhance each other at the output; in the above example, each path forces Vout to increase.

VCC

I EE

Figure 10.51 Signal paths in pair with active load.

Our initial examination of Q3 and Q4 in Fig. 10.50 indicates an interesting difference with respect to current mirrors studied in Chapter 9: here Q3 and Q4 carry signals in addition to bias currents. This also stands in contrast to the current-source loads in Fig. 10.52, where the baseemitter voltage of the load transistors remains constant and independent of signals. Called an “active load” to distinguish it from the load transistors in Fig. 10.52, the combination of Q3 and Q4 plays a critical role in the operation of the circuit.

P

I EE

(a)

Figure 10.52 Differential pair with current-source loads.

The foregoing analysis directly applies to the CMOS counterpart, shown in Fig. 10.53. Specifically, in response to a small, differential input, ID1 rises to ISS=2 + I and ID2 falls to ISS=2 , I. The change in ID2 tends to raise Vout. Also, the change in ID1 and ID3 is copied into ID4, increasing jID4j and raising Vout. (In this circuit, too, the current mirror transistors are identical.)

10.6.2 Quantitative Analysis

The existence of the signal paths in the differential to single-ended converter circuit suggests that the voltage gain of the circuit must be greater than that of a differential topology in which only one output node is sensed with respect to ground [e.g., Fig. 10.47(b)]. To confirm this conjecture, we wish to determine the small-signal single-ended output, vout, divided by the smallsignal differential input, vin1 , vin2. We deal with a CMOS implementation here (Fig. 10.54) to demonstrate that both CMOS and bipolar versions are treated identically.

I SS

Figure 10.53 MOS differential pair with active load.

Figure 10.54 MOS pair for small-signal analysis.

The circuit of Fig. 10.54 presents a quandary. While the transistors themselves are symmetric and the input signals are small and differential, the circuit is asymmetric. With the diodeconnected device, M3, creating a low impedance at node A, we expect a relatively small voltage swing—on the order of the input swing—at this node. On the other hand, transistors M2 and M4 provide a high impedance and hence a large voltage swing at the output node. (After all, the circuit serves as an amplifier .) The asymmetry resulting from the very different voltage swings at the drains of M1 and M2 disallows grounding node P for small-signal analysis. We present two approaches to solving this circuit.

Approach I Without a half circuit available, the analysis can be performed through the use of a complete small-signal model of the amplifier. Referring to the equivalent circuit shown in Fig. 10.55, where the dashed boxes indicate each transistor, we perform the analysis in two steps. In

Figure 10.55 (a) Small-signal equivalent circuit of differential pair with active load.

the first step, we note that iX and iY must add up to zero at node P and hence iX = ,iY . Also,

514 Chap. 10 Differential Amplifiers

In the second step, we write a KVL around the loop consisting of all four transistors. The current through rON of M1 is equal to iX , gmN v1 and that through rON of M2 equal to iY , gmN v2. It follows that

The gain is indepedent of gmP and equal to that of the fully-differential circuit. In other words, the use of the active load has restored the gain.

Approach II In this approach, we decompose the circuit into sections that more easily lend themselves to analysis by inspection. As illustrated in Fig. 10.56(a), we first seek a Thevenin equivalent for the section consisting of vin1, vin2, M1 and M2, assuming vin1 and vin2 are differential. Recall that vT hev is the voltage between A and B in the “open-circuit condition”

This section can be skipped in a first reading.

[Fig. 10.56(b)]. Under this condition, the circuit is symmetric, resembling the topology of Fig. 10.16(a). Equation (10.92) thus yields

Figure 10.56 (a) Thevenin equivalent, (b) Thevenin voltage, and (c) Thevenin resistance of input pair.

To determine the Thevenin resistance, we set the inputs to zero and apply a voltage between the output terminals [Fig. 10.56(c)]. Noting that M1 and M2 have equal gate-source voltages (v1 = v2) and writing a KVL around the “output” loop, we have

and hence

The reader is encouraged to obtain this result using half circuits as well.

Having reduced the input sources and transistors to a Thevenin equivalent, we now compute the gain of the overall amplifier. Figure 10.57 depicts the simplified circuit, where the diodeconnected transistor M3 is replaced with (1=gm3)jjrO3 and the output impedance of M4 is drawn explicitly. The objective is to calculate vout in terms of vT hev. Since the voltage at node E with respect to ground is equal to vout + vT hev, we can view vA as a divided version of vE:

VDD

r O3 g1

m3

M 4

v out

E

Figure 10.57 Simplified circuit for calculation of voltage gain.

Given by gm4vA, the small-signal drain current of M4 must satisfy KCL at the output node:

where the last term on the left hand side represents the current flowing through RT hev. It follows from (10.204) and (10.205) that

Recognizing that 1=gm3 rO3, and 1=gm3 RT hev and assuming gm3 = gm4 = gmp and rO3 = rO4 = rOP , we reduce (10.206) to

The gain is independent of gmp. Interestingly, the gain of this circuit is the same as the differential gain of the topology in Fig. 10.51(b). In other words, the path through the active load restores the gain even though the output is single-ended.

Example 10.29

In our earlier observations, we surmised that the voltage swing at node A in Fig. 10.56 is much less than that at the output. Prove this point.

Solution

As depicted in Fig. 10.58, KCL at the output node indicates that the total current drawn by M2 must be equal to ,vout=rO4 , gm4vA. This current flows through M1 and hence through M3, generating

Sec. 10.7 Chapter Summary 517

revealing that vA is indeed much less that vout.

A

v out

P

I SS

Figure 10.58

Exercise

Calculate the voltage gain from the differential input to node A.

10.7 Chapter Summary

Single-ended signals are voltages measured with respect to ground. A differential signal consists of two single-ended signals carried over two wires, with the two components beginning from the same dc (common-mode) level and changing by equal and opposite amounts.

Compared with single-ended signals, differential signals are more immune to common-mode noise.

The transistor currents change in opposite directions if a differential input is applied, i.e., the circuit responds to differential inputs.

For small, differential changes at the input, the tail node voltage of a differential pair remains constant and is thus considered a virtual ground node.

Bipolar differential pairs exhibit a hyperbolic tangent input/output characteristic. The tail current can be mostly steered to one side with a differential input of about 4VT .

For small-signal operation, the input differential swing of a bipolar differential pair must remain below roughly VT . The pair can then be decomposed into two half circuits, each of which is simply a common-emitter stage.

MOS differential pairs can steer the tail current with a differential input equal to p2ISS=( nCoxW=L), which is p2 larger than the equilibrium overdrive of each transistor.

Problems

1.To calculate the effect of ripple at the output of the circuit in Fig. 10.1, we can assume VCC is a small-signal “input” and determine the (small-signal) gain from VCC to Vout. Compute this gain, assuming VA < 1.

2.Repeat Problem 1 for the circuit of Fig. 10.2(a), assuming RC1 = RC2.

3.Repeat Problem 1 for the stages shown in Fig. 10.59. Assume VA < 1 and > 0.

Figure 10.59

4. In the circuit of Fig. 10.60, I1 = I0 cos !t+I0 and I2 = ,I0 cos !t+I0. Plot the waveforms

Figure 10.60

at X and Y and determine their peak-to-peak swings and common-mode level.

5.Repeat Problem 4 for the circuit depicted in Fig. 10.61. Also, plot the voltage at node P as a function of time.

6.Repeat Problem 4 for the topology shown in Fig. 10.62.

7.Repeat Problem 4 for the topology shown in Fig. 10.63.

Figure 10.63

8.Repeat Problem 4, but assume I2 = ,I0 cos !t + 0:8I0. Can X and Y be considered true differential signals?

9.Assuming I1 = I0 cos !t + I0 and I2 = ,I0 cos !t + I0, plot VX and VY as a function of time for the circuits illustrated in Fig. 10.64. Assume I1 is constant.

Figure 10.64

10.Assuming V1 = V0 cos !t + V0 and V2 = ,V0 cos !t + V0, plot VP as a function of time for the circuits shown in Fig. 10.65. Assume IT is constant.

Figure 10.65

11.Suppose in Fig. 10.7, VCC rises by V . Neglecting the Early effect, determine the change in VX , VY , and VX , VY . Explain why we say the circuit “rejects” supply noise.

12.In Fig. 10.7, IEE experiences a change of I. How do VX , VY , and VX , VY change?

13.Repeat Problem 12, but assuming that RC1 = RC2 + R. Neglect the Early effect.

14.Consider the circuit of Fig. 10.9(a) and assume IEE = 1 mA. What is the maximum allowable value of RC if Q1 must remain in the active region?

15.In the circuit of Fig. 10.9(b), RC = 500 . What is the maximum allowable value of IEE if Q2 must remain in the active region?

16.Suppose IEE = 1 mA and RC = 800 in Fig. 10.9(a). Determine the region of operation of Q1.

17.What happens to the characteristics depicted in Fig. 10.10 if (a) IEE is halved, (b) VCC rises by V , or (c) RC is halved?

18.In the differential pair of Fig. 10.12, IC1 =IC2 = 5. What is the corresponding input differential voltage? With this voltage applied, how does IC1=IC2 change if the temperature rises from 27 C to 100 C?

19.Suppose the input differential signal applied to a bipolar differential pair must not change the transconductance (and hence the bias current) of each transistor by more than 10%. From Eq. (10.58), determine the maximum allowable input.

20.In the circuit of Fig. 10.12, the small-signal transconductance of Q2 falls as Vin1 , Vin2 rises because IC2 decreases. Using Eq. (10.58), determine the input difference at which the transconductance of Q2 drops by a factor of 2.

21.It is possible to define a differential transconductance for the bipolar differential pair of Fig. 10.12:

From Eqs. (10.58) and (10.60), compute Gm and plot the result as a function of Vin1 , Vin2. What is the maximum value of Gm? At what value of Vin1 , Vin2 does Gm drop by a factor of two with respect to its maximum value?

22.With the aid of Eq. (10.78), we can compute the small-signal voltage gain of the bipolar differential pair:

Determine the gain and compute its value if Vin1 , Vin2 contains a dc component of 30 mV.

23.Explain what happens to the characteristics shown in Fig. 10.13 if the ambient temperature goes from 27 C to 100 C.