Fundamentals of Microelectronics

57. The bipolar cascode amplifier of Fig. 9.74 must be designed for a voltage gain of 500. Use

VCC

I 1

Vout

Vb1Q 2

VinQ 1

Figure 9.74

Eq. (9.53) and assume = 100.

(a)What is the minimum required value of VA?

(b)For a bias current of 0.5 mA, calculate the required bias component in Vin.

(c)Compute the value of Vb1 such that Q1 sustains a collector-emitter voltage of 500 mV.

58.Design the cascode amplifier shown in Fig. 9.75 for a power budget of 2 mW. Select Vb1 and

VCC = 2.5 V

Vb3 Q 4

Vb2 Q 3

Vout

Vb1Q 2

VinQ 1

Figure 9.75

Vb2 such that Q1 and Q4 sustain a base-collector forward bias of 200 mV. What voltage gain is achieved?

59. Design the CMOS cascode amplifier of Fig. 9.76 for a voltage gain of 200 and a power

Figure 9.76

= 1:8 V. Assume (W=L)1 = = (W=L)4 = 20=0:18 and

p = 2 n = 0:2 V,1. Determine the required dc levels of Vin and Vb3. For simplicity, assume Vb1 = Vb2 = 0:9 V.

60.The current mirror shown in Fig. 9.77 must deliver I1 = 0:5 mA to a circuit with a total power budget of 2 mW. Assuming VA = 1 and 1, determine the required value of IREF and the relative sizes of QREF and Q1.

VCC = 2.5 V

Circuit

I REF

I 1

Figure 9.77

61. In the circuit of Fig. 9.78, Q2 operates as an emitter follower. Design the circuit for a power

Figure 9.78

budget of 3 mW and an output impedance of 50 . Assume VA = 1 and 1.

62. In the circuit of Fig. 9.79, Q2 operates as a common-base stage. Design the circuit for an

Figure 9.79

output impedance of 500 , a voltage gain of 20, and a power budget of 3 mW. Assume VA = 1 and 1.

63.Design the circuit of Fig. 9.30 for Icopy = 0:5 mA and an error of less than 1% with respect to the nominal value. Explain the trade-off between accuracy and power dissipation in this circuit. Assume VCC = 2:5 V.

64.Design the circuit of Fig. 9.34 such that the bias current of Q2 is 1 mA and the error in IC1 with respect to its nominal value is less than 2%. Is the solution unique?

65.Figure 9.80 shows an arrangement where M1 and M2 serve as current sources for circuits 1 and 2. Design the circuit for a power budget of 3 mW.

66.The common-source stage depicted in Fig. 9.81 must be designed for a voltage gain of 20 and a power budget of 2 mW. Assuming (W=L)1 = 20=0:18, n = 0:1 V,1, and p = 0:2 V,1, design the circuit.

67.The source follower of Fig. 9.82 must achieve a voltage gain of 0.85 and an output impedance of 100 . Assuming (W=L)2 = 10=0:18, n = 0:1 V,1, and p = 0:2 V,1, design the circuit.

Figure 9.81

VDD = 1.8 V

Vout

Figure 9.82

68. The common-gate stage of Fig. 9.83 employs the current source M3 as the load to achieve

Figure 9.83

a high voltage gain. For simplicity, neglect channel-length modulation in M1. Assuming (W=L)3 = 40=0:18, n = 0:1 V,1, and p = 0:2 V,1, design the circuit for a voltage gain of 20, an input impedance of 50 , and a power budget of 13 mW. (You may not need all of the power budget.)

SPICE Problems

464 Chap. 9 Cascode Stages and Current Mirrors

In the following problems, use the MOS device models given in Appendix A. For bipolar transistors, assume IS;npn = 5 10,16 A, npn = 100, VA;npn = 5 V, IS;pnp = 8 10,16

A, pnp = 50, VA;pnp = 3:5 V.

69.In the circuit of Fig. 9.84, we wish to suppress the error due to the base currents by means of resistor RP .

Figure 9.84

(a)Tying the collector of Q2 to VCC, select the value of RP so as to minimize the error between I1 and IREF .

(b)What is the change in the error if the of both transistors varies by 3%?

(c)What is the change in the error if RP changes by 10%?

70.Repeat Problem 69 for the circuit shown in Fig. 9.85. Which circuit exhibits less sensitivity to variations in and RP ?

RP

Figure 9.85

71.Figure 9.86 depicts a cascode current source whose value is defined by the mirror arrangement, M1-M2. Assume W=L = 5 m=0:18 m for M1-M3.

VDD = 1.8 V

I out

0.5 mA

VbM 3

M 2

M 1

Figure 9.86

(a)Select the value of Vb so that Iout is precisely equal to 0.5 mA.

(b)Determine the change in Iout if Vb varies by 100 mV. Explain the cause of this change.

(c)Using both hand analysis and SPICE simulations, determine the output impedance of the cascode and compare the results.

72.We wish to study the problem of biasing in a high-gain cascode stage, Fig. 9.87. Assume (W=L)1;2 = 10 m=0:18 mum, Vb = 0:9 V, and I1 = 1 mA is an ideal current source.

(a)Plot the input/output characteristic and determine the value of Vin at which the slope (small-signal gain) reaches a maximum.

VDD = 1.8 V

I 1

Vout

VbM 2

VinM 1

Figure 9.87

(b) Now, suppose the biasing circuitry that must produce the above dc value for Vin incurs an error of 20 mV. From (a), explain what happens to the small-signal gain.

73.Repeat Problem 72 for the cascode shown in Fig. 9.88, assuming W=L = 10 m=0:18 m for all of the transistors.

VDD = 1.8 V

M 5 M 4

VbVout

M 2

VinM 1

Figure 9.88

References

1. B. Razavi, Design of Analog CMOS Integrated Circuits McGraw-Hill, 2001.

Differential Amplifiers

The elegant concept of “differential” signals and amplifiers was invented in the 1940s and first utilized in vacuum-tube circuits. Since then, differential circuits have found increasingly wider usage in microelectronics and serve as a robust, high-performance design paradigm in many of today's systems. This chapter describes bipolar and MOS differential amplifiers and formulates their large-signal and small-signal properties. The concepts are outlined below.

10.1 General Considerations

10.1.1 Initial Thoughts

In order to understand the need for differential circuits, let us first consider an example.

Example 10.1

Having learned the design of rectifiers and basic amplifier stages, an electrical engineering student constructs the circuit shown in Fig. 10.1(a) to amplify the signal produced by a microphone. Unfortunately, upon applying the result to a speaker, the student observes that the amplifier output contains a strong “humming” noise, i.e., a steady low-frequency component. Explain what happens.

Solution

Recall from Chapter 3 that the current drawn from the rectified output creates a ripple waveform at twice the ac line frequency (50 or 60 Hz) [Fig. 10.1(b)]. Examining the output of the commonemitter stage, we can identify two components: (1) the amplified version of the microphone signal and (2) the ripple waveform present on VCC. For the latter, we can write

noting that Vout simply “tracks” VCC and hence contains the ripple in its entirety. The “hum” originates from the ripple. Figure 10.1(c) depicts the overall output in the presence of both the signal and the ripple. Illustrated in Fig. 10.1(d), this phenomenon is summarized as the “supply

466

VCC

Vout

Signal

Figure 10.1 (a) CE stage powered by a rectifier, (b) ripple on supply voltage, (c) effect at output, (d) ripple and signal paths to output.

noise goes to the output with a gain of unity.” (A MOS implementation would suffer from the same problem.)

Exercise

What is the hum frequency for a full-wave rectifier or a half-wave rectifier?

How should we suppress the hum in the above example? We can increase C1, thus lowering the ripple amplitude, but the required capacitor value may become prohibitively large if many circuits draw current from the rectifier. Alternatively, we can modify the amplifier topology such that the output is insensitive to VCC. How is that possible? Equation (10.1) implies that a change in VCC directly appears in Vout, fundamentally because both Vout and VCC are measured with respect to ground and differ by RCIC. But what if Vout is not “referenced” to ground?! More specifically, what if Vout is measured with respect to another point that itself experiences the supply ripple to the same extent? It is thus possible to eliminate the ripple from the “net” output.

While rather abstract, the above conjecture can be readily implemented. Figure 10.2(a) illustrates the core concept. The CE stage is duplicated on the right, and the output is now measured between nodes X and Y rather than from X to ground. What happens if VCC contains ripple? Both VX and VY rise and fall by the same amount and hence the difference between VX and VY remains free from the ripple.

In fact, denoting the ripple by vr, we express the small-signal voltages at these nodes as

Figure 10.2 Use of two CE stages to remove effect of ripple.

The above development serves as the foundation for differential amplifiers: the symmetric CE stages provide two output nodes whose voltage difference remains free from the supply ripple.

10.1.2 Differential Signals

Let us return to the circuit of Fig. 10.2(a) and recall that the duplicate stage consisting of Q2 and RC2 remains “idle,” thereby “wasting” current. We may therefore wonder if this stage can provide signal amplification in addition to establishing a reference point for Vout. In our first attempt, we directly apply the input signal to the base of Q2 [Fig. 10.3(a)]. Unfortunately, the signal components at X and Y are in phase, canceling each other as they appear in vX , vY :

(c)

Figure 10.3 (a) Application of one input signal to two CE stages, (b) use of differential input signals, (c) generation of differential phases from one signal.

For the signal components to enhance each other at the output, we can invert one of the input

470 Chap. 10 Differential Amplifiers

Since each of V1 and V2 has a peak-to-peak swing of 2V0, we say the “differential swing” is 4V0. We may also say V1 and V2 are differential signals to emphasize that they vary by equal and opposite amounts around a fixed level, VCM .

The dc voltage that is common to both V1 and V2 [VCM in Fig. 10.4(c)] is called the “commonmode (CM) level.” That is, in the absence of differential signals, the two nodes remain at a potential equal to VCM with respect to the global ground. For example, in the transformer of Fig. 10.3(c), +vin and ,vin display a CM level of zero because the center tap of the transformer is grounded.

Example 10.2

How can the transformer of Fig. 10.3(c) produce an output CM level equal to +2 V.

Solution

The center tap can simply be tied to a voltage equal to +2 V (Fig. 10.5).

t

Figure 10.5

Exercise

Does the CM level change if the inputs of the amplifier draw a bias current?

Example 10.3

Determine the common-mode level at the output of the circuit shown in Fig. 10.3(b).

Solution

In the absence of signals, VX = VY = VCC , RCIC (with respect to ground), where RC = RC1 = RC2 and IC denotes the bias current of Q1 and Q2. Thus, VCM = VCC , RCIC. Interestingly, the ripple affects VCM but not the differential output.

Exercise

If a resistor of value R1 is inserted between VCC and the top terminals of RC1 and RC2, what is the output CM level?

Our observations regarding supply ripple and the use of the “duplicate stage” provide sufficient justification for studying differential signals. But, how about the common-mode level? What is the significance of VCM = VCC , RCIC in the above example? Why is it interesting that the ripple appears in VCM but not in the differential output? We will answer these important questions in the following sections.