INSTRUCTION SET REFERENCE - VEX-ENCODED GPR INSTRUCTIONS

BZHI - Zero High Bits Starting with Specified Bit Position

NOTES:

1.ModRM:r/m is used to encode the first source operand (second operand) and VEX.vvvv encodes the second source operand (third operand).

Instruction Operand Encoding

Description

BZHI copies the bits of the first source operand (the second operand) into the destination operand (the first operand) and clears the higher bits in the destination according to the INDEX value specified by the second source operand (the third operand). The INDEX is specified by bits 7:0 of the second source operand. The INDEX value is saturated at the value of OperandSize -1. CF is set, if the number contained in the 8 low bits of the third operand is greater than OperandSize -1.

This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.

Operation

N ← SRC2[7:0]

DEST ← SRC1

IF (N < OperandSize)

DEST[OperandSize-1:N] ← 0

FI

IF (N > OperandSize - 1)

CF ← 1

ELSE

CF ← 0

INSTRUCTION SET REFERENCE - VEX-ENCODED GPR INSTRUCTIONS

FI

Flags Affected

ZF, CF and SF flags are updated based on the result. OF flag is cleared. AF and PF flags are undefined.

Intel C/C++ Compiler Intrinsic Equivalent

BZHI unsigned __int32 _bzhi_u32(unsigned __int32 src, unsigned __int32 index); BZHI unsigned __int64 _bzhi_u64(unsigned __int64 src, unsigned __int32 index);

SIMD Floating-Point Exceptions

None

Other Exceptions

See Table 2-22.

INSTRUCTION SET REFERENCE - VEX-ENCODED GPR INSTRUCTIONS

LZCNT— Count the Number of Leading Zero Bits

Instruction Operand Encoding

Description

Counts the number of leading most significant zero bits in a source operand (second operand) returning the result into a destination (first operand).

LZCNT is an extension of the BSR instruction. The key difference between LZCNT and BSR is that LZCNT provides operand size as output when source operand is zero, while in the case of BSR instruction, if source operand is zero, the content of destination operand are undefined. On processors that do not support LZCNT, the instruction byte encoding is executed as BSR.

In 64-bit mode 64-bit operand size requires REX.W=1.

Operation

temp ← OperandSize - 1 DEST ← 0

WHILE (temp >= 0) AND (Bit(SRC, temp) = 0) DO

temp ← temp - 1 DEST ← DEST+ 1

OD

IF DEST = OperandSize

CF ← 1

ELSE

INSTRUCTION SET REFERENCE - VEX-ENCODED GPR INSTRUCTIONS

CF ← 0

FI

IF DEST = 0

ZF ← 1

ELSE

ZF ← 0

FI

Flags Affected

ZF flag is set to 1 in case of zero output (most significant bit of the source is set), and to 0 otherwise, CF flag is set to 1 if input was zero and cleared otherwise. OF, SF, PF and AF flags are undefined.

Intel C/C++ Compiler Intrinsic Equivalent

LZCNT unsigned __int32 _lzcnt_u32(unsigned __int32 src);

LZCNT unsigned __int64 _lzcnt_u64(unsigned __int64 src);

SIMD Floating-Point Exceptions

None

Other Exceptions

See Table 2-21.

INSTRUCTION SET REFERENCE - VEX-ENCODED GPR INSTRUCTIONS

MULX — Unsigned Multiply Without Affecting Flags

Instruction Operand Encoding

Description

Performs an unsigned multiplication of the implicit source operand (EDX/RDX) and the specified source operand (the third operand) and stores the low half of the result in the second destination (second operand), the high half of the result in the first destination operand (first operand), without reading or writing the arithmetic flags. This enables efficient programming where the software can interleave add with carry operations and multiplications.

If the first and second operand are identical, it will contain the high half of the multiplication result.

This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.

Operation

//DEST1: ModRM:reg

//DEST2: VEX.vvvv IF (OperandSize = 32)

SRC1 ← EDX;

DEST2 ← (SRC1*SRC2)[31:0]; DEST1 ← (SRC1*SRC2)[63:32];

ELSE IF (OperandSize = 64) SRC1 ← RDX;

DEST2 ← (SRC1*SRC2)[63:0];

INSTRUCTION SET REFERENCE - VEX-ENCODED GPR INSTRUCTIONS

DEST1 ← (SRC1*SRC2)[127:64];

FI

Flags Affected

None

Intel C/C++ Compiler Intrinsic Equivalent

Auto-generated from high-level language.

SIMD Floating-Point Exceptions

None

Other Exceptions

See Table 2-22.

INSTRUCTION SET REFERENCE - VEX-ENCODED GPR INSTRUCTIONS

PDEP — Parallel Bits Deposit

Instruction Operand Encoding

Description

PDEP uses a mask in the second source operand (the third operand) to transfer/scatter contiguous low order bits in the first source operand (the second operand) into the destination (the first operand). PDEP takes the low bits from the first source operand and deposit them in the destination operand at the corresponding bit locations that are set in the second source operand (mask). All other bits (bits not set in mask) in destination are set to zero.

Figure 7-1. PDEP Example

INSTRUCTION SET REFERENCE - VEX-ENCODED GPR INSTRUCTIONS

This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.

Operation

TEMP ← SRC1;

MASK ← SRC2; DEST ← 0 ; m← 0, k← 0;

DO WHILE m< OperandSize

IF MASK[ m] = 1 THEN DEST[ m] ← TEMP[ k]; k ← k+ 1;

FI

m ← m+ 1;

OD

Flags Affected

None.

Intel C/C++ Compiler Intrinsic Equivalent

PDEP unsigned __int32 _pdep_u32(unsigned __int32 src, unsigned __int32 mask);

PDEP unsigned __int64 _pdep_u64(unsigned __int64 src, unsigned __int32 mask);

SIMD Floating-Point Exceptions

None

Other Exceptions

See Table 2-22.

INSTRUCTION SET REFERENCE - VEX-ENCODED GPR INSTRUCTIONS

PEXT— Parallel Bits Extract

Instruction Operand Encoding

Description

PEXT uses a mask in the second source operand (the third operand) to transfer either contiguous or non-contiguous bits in the first source operand (the second operand) to contiguous low order bit positions in the destination (the first operand). For each bit set in the MASK, PEXT extracts the corresponding bits from the first source operand and writes them into contiguous lower bits of destination operand. The remaining upper bits of destination are zeroed.

Figure 7-2. PEXT Example

INSTRUCTION SET REFERENCE - VEX-ENCODED GPR INSTRUCTIONS

This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.

Operation

TEMP ← SRC1;

MASK ← SRC2; DEST ← 0 ; m← 0, k← 0;

DO WHILE m< OperandSize

IF MASK[ m] = 1 THEN DEST[ k] ← TEMP[ m]; k ← k+ 1;

FI

m ← m+ 1;

OD

Flags Affected

None.

Intel C/C++ Compiler Intrinsic Equivalent

PEXT unsigned __int32 _pext_u32(unsigned __int32 src, unsigned __int32 mask);

PEXT unsigned __int64 _pext_u64(unsigned __int64 src, unsigned __int32 mask);

SIMD Floating-Point Exceptions

None

Other Exceptions

See Table 2-22.

INSTRUCTION SET REFERENCE - VEX-ENCODED GPR INSTRUCTIONS

RORX — Rotate Right Logical Without Affecting Flags

Instruction Operand Encoding

Description

Rotates the bits of second operand right by the count value specified in imm8 without affecting arithmetic flags. The RORX instruction does not read or write the arithmetic flags.

This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.

Operation

IF (OperandSize = 32)

y ← imm8 AND 1FH;

DEST ← (SRC >> y) | (SRC << (32-y)); ELSEIF (OperandSize = 64 )

y ← imm8 AND 3FH;

DEST ← (SRC >> y) | (SRC << (64-y)); ENDIF

Flags Affected

None

Intel C/C++ Compiler Intrinsic Equivalent

Auto-generated from high-level language.

INSTRUCTION SET REFERENCE - VEX-ENCODED GPR INSTRUCTIONS

SIMD Floating-Point Exceptions

None

Other Exceptions

See Table 2-22.

INSTRUCTION SET REFERENCE - VEX-ENCODED GPR INSTRUCTIONS

SARX/SHLX/SHRXShift Without Affecting Flags

NOTES:

1.ModRM:r/m is used to encode the first source operand (second operand) and VEX.vvvv encodes the second source operand (third operand).

Instruction Operand Encoding

Description

Shifts the bits of the first source operand (the second operand) to the left or right by a COUNT value specified in the second source operand (the third operand). The result is written to the destination operand (the first operand).

The shift arithmetic right (SARX) and shift logical right (SHRX) instructions shift the bits of the destination operand to the right (toward less significant bit locations), SARX keeps and propagates the most significant bit (sign bit) while shifting.

The logical shift left (SHLX) shifts the bits of the destination operand to the left (toward more significant bit locations).

INSTRUCTION SET REFERENCE - VEX-ENCODED GPR INSTRUCTIONS

This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.

If the value specified in the first source operand exceeds OperandSize -1, the COUNT value is masked.

SARX,SHRX, and SHLX instructions do not update flags.

Operation

TEMP ← SRC1;

IF VEX.W1 and CS.L = 1 THEN

countMASK ←3FH; ELSE

countMASK ←1FH;

FI

COUNT ← (SRC2 AND countMASK)

DEST[OperandSize -1] = TEMP[OperandSize -1];

DO WHILE (COUNT != 0)

IF instruction is SHLX

THEN

DEST[] ← DEST *2;

ELSE IF instruction is SHRX

THEN

DEST[] ← DEST /2; // signed divide, round toward negative infinity

FI;

COUNT ← COUNT - 1;

OD

Flags Affected

None.

Intel C/C++ Compiler Intrinsic Equivalent

Auto-generated from high-level language.

SIMD Floating-Point Exceptions

None

INSTRUCTION SET REFERENCE - VEX-ENCODED GPR INSTRUCTIONS

Other Exceptions

See Table 2-22.

INSTRUCTION SET REFERENCE - VEX-ENCODED GPR INSTRUCTIONS

TZCNT — Count the Number of Trailing Zero Bits

Instruction Operand Encoding

Description

TZCNT counts the number of trailing least significant zero bits in source operand (second operand) and returns the result in destination operand (first operand). TZCNT is an extension of the BSF instruction. The key difference between TZCNT and BSF instruction is that TZCNT provides operand size as output when source operand is zero while in the case of BSF instruction, if source operand is zero, the content of destination operand are undefined. On processors that do not support TZCNT, the instruction byte encoding is executed as BSF.

Operation

temp ← 0 DEST ← 0

DO WHILE ( (temp < OperandSize) and (SRC[ temp] = 0) )

temp ← temp +1 DEST ← DEST+ 1

OD

IF DEST = OperandSize

CF ← 1

ELSE

CF ← 0

FI

INSTRUCTION SET REFERENCE - VEX-ENCODED GPR INSTRUCTIONS

IF DEST = 0

ZF ← 1

ELSE

ZF ← 0

FI

Flags Affected

ZF is set to 1 in case of zero output (least significant bit of the source is set), and to 0 otherwise, CF is set to 1 if the input was zero and cleared otherwise. OF, SF, PF and AF flags are undefined.

Intel C/C++ Compiler Intrinsic Equivalent

TZCNT unsigned __int32 _tzcnt_u32(unsigned __int32 src);

TZCNT unsigned __int64 _tzcnt_u64(unsigned __int64 src);

SIMD Floating-Point Exceptions

None

Other Exceptions

See Table 2-21.