- •Chapter 1 Intel® Advanced Vector Extensions
- •1.1 About This Document
- •1.2 Overview
- •1.3.2 Instruction Syntax Enhancements
- •1.3.3 VEX Prefix Instruction Encoding Support
- •1.4 Overview AVX2
- •1.5 Functional Overview
- •1.6 General Purpose Instruction Set Enhancements
- •2.1 Detection of PCLMULQDQ and AES Instructions
- •2.2 Detection of AVX and FMA Instructions
- •2.2.1 Detection of FMA
- •2.2.3 Detection of AVX2
- •2.3.1 FMA Instruction Operand Order and Arithmetic Behavior
- •2.4 Accessing YMM Registers
- •2.5 Memory alignment
- •2.7 Instruction Exception Specification
- •2.7.1 Exceptions Type 1 (Aligned memory reference)
- •2.7.2 Exceptions Type 2 (>=16 Byte Memory Reference, Unaligned)
- •2.7.3 Exceptions Type 3 (<16 Byte memory argument)
- •2.7.5 Exceptions Type 5 (<16 Byte mem arg and no FP exceptions)
- •2.7.7 Exceptions Type 7 (No FP exceptions, no memory arg)
- •2.7.8 Exceptions Type 8 (AVX and no memory argument)
- •2.8.1 Clearing Upper YMM State Between AVX and Legacy SSE Instructions
- •2.8.3 Unaligned Memory Access and Buffer Size Management
- •2.9 CPUID Instruction
- •3.1 YMM State, VEX Prefix and Supported Operating Modes
- •3.2 YMM State Management
- •3.2.1 Detection of YMM State Support
- •3.2.2 Enabling of YMM State
- •3.2.4 The Layout of XSAVE Area
- •3.2.5 XSAVE/XRSTOR Interaction with YMM State and MXCSR
- •3.2.6 Processor Extended State Save Optimization and XSAVEOPT
- •3.2.6.1 XSAVEOPT Usage Guidelines
- •3.3 Reset Behavior
- •3.4 Emulation
- •4.1 Instruction Formats
- •4.1.1 VEX and the LOCK prefix
- •4.1.2 VEX and the 66H, F2H, and F3H prefixes
- •4.1.3 VEX and the REX prefix
- •4.1.4 The VEX Prefix
- •4.1.4.1 VEX Byte 0, bits[7:0]
- •4.1.4.2 VEX Byte 1, bit [7] - ‘R’
- •4.1.5 Instruction Operand Encoding and VEX.vvvv, ModR/M
- •4.1.6 The Opcode Byte
- •4.1.7 The MODRM, SIB, and Displacement Bytes
- •4.1.8 The Third Source Operand (Immediate Byte)
- •4.1.9.1 Vector Length Transition and Programming Considerations
- •4.1.10 AVX Instruction Length
- •4.2 Vector SIB (VSIB) Memory Addressing
- •4.3 VEX Encoding Support for GPR Instructions
- •5.1 Interpreting InstructIon Reference Pages
- •5.1.1 Instruction Format
- •5.1.2 Opcode Column in the Instruction Summary Table
- •5.1.3 Instruction Column in the Instruction Summary Table
- •5.1.4 Operand Encoding column in the Instruction Summary Table
- •5.1.5 64/32 bit Mode Support column in the Instruction Summary Table
- •5.1.6 CPUID Support column in the Instruction Summary Table
- •5.2 Summary of Terms
- •5.3 Instruction SET Reference
- •MPSADBW - Multiple Sum of Absolute Differences
- •PALIGNR - Byte Align
- •PBLENDW - Blend Packed Words
- •PHADDW/PHADDD - Packed Horizontal Add
- •PHADDSW - Packed Horizontal Add with Saturation
- •PHSUBW/PHSUBD - Packed Horizontal Subtract
- •PHSUBSW - Packed Horizontal Subtract with Saturation
- •PMOVSX - Packed Move with Sign Extend
- •PMOVZX - Packed Move with Zero Extend
- •PMULDQ - Multiply Packed Doubleword Integers
- •PMULHRSW - Multiply Packed Unsigned Integers with Round and Scale
- •PMULHUW - Multiply Packed Unsigned Integers and Store High Result
- •PMULHW - Multiply Packed Integers and Store High Result
- •PMULLW/PMULLD - Multiply Packed Integers and Store Low Result
- •PMULUDQ - Multiply Packed Unsigned Doubleword Integers
- •POR - Bitwise Logical Or
- •PSADBW - Compute Sum of Absolute Differences
- •PSHUFB - Packed Shuffle Bytes
- •PSHUFD - Shuffle Packed Doublewords
- •PSHUFLW - Shuffle Packed Low Words
- •PSIGNB/PSIGNW/PSIGND - Packed SIGN
- •PSLLDQ - Byte Shift Left
- •PSLLW/PSLLD/PSLLQ - Bit Shift Left
- •PSRAW/PSRAD - Bit Shift Arithmetic Right
- •PSRLDQ - Byte Shift Right
- •PSRLW/PSRLD/PSRLQ - Shift Packed Data Right Logical
- •PSUBB/PSUBW/PSUBD/PSUBQ -Packed Integer Subtract
- •PSUBSB/PSUBSW -Subtract Packed Signed Integers with Signed Saturation
- •PSUBUSB/PSUBUSW -Subtract Packed Unsigned Integers with Unsigned Saturation
- •PXOR - Exclusive Or
- •VPBLENDD - Blend Packed Dwords
- •VPERMD - Full Doublewords Element Permutation
- •VPERMPD - Permute Double-Precision Floating-Point Elements
- •VPERMPS - Permute Single-Precision Floating-Point Elements
- •VPERMQ - Qwords Element Permutation
- •VPSLLVD/VPSLLVQ - Variable Bit Shift Left Logical
- •VPSRAVD - Variable Bit Shift Right Arithmetic
- •VPSRLVD/VPSRLVQ - Variable Bit Shift Right Logical
- •VGATHERDPD/VGATHERQPD - Gather Packed DP FP values Using Signed Dword/Qword Indices
- •VGATHERDPS/VGATHERQPS - Gather Packed SP FP values Using Signed Dword/Qword Indices
- •VPGATHERDD/VPGATHERQD - Gather Packed Dword values Using Signed Dword/Qword Indices
- •VPGATHERDQ/VPGATHERQQ - Gather Packed Qword values Using Signed Dword/Qword Indices
- •6.1 FMA InstructIon SET Reference
- •Chapter 7 Instruction Set Reference - VEX-Encoded GPR Instructions
- •7.1 Instruction Format
- •7.2 INSTRUCTION SET REFERENCE
- •BZHI - Zero High Bits Starting with Specified Bit Position
- •INVPCID - Invalidate Processor Context ID
- •Chapter 8 Post-32nm Processor Instructions
- •8.1 Overview
- •8.2 CPUID Detection of New Instructions
- •8.4 Vector Instruction Exception Specification
- •8.6 Using RDRAND Instruction and Intrinsic
- •8.7 Instruction Reference
- •A.1 AVX Instructions
- •A.2 Promoted Vector Integer Instructions in AVX2
- •B.1 Using Opcode Tables
- •B.2 Key to Abbreviations
- •B.2.1 Codes for Addressing Method
- •B.2.2 Codes for Operand Type
- •B.2.3 Register Codes
- •B.2.4 Opcode Look-up Examples for One, Two, and Three-Byte Opcodes
- •B.2.4.1 One-Byte Opcode Instructions
- •B.2.4.2 Two-Byte Opcode Instructions
- •B.2.4.3 Three-Byte Opcode Instructions
- •B.2.4.4 VEX Prefix Instructions
- •B.2.5 Superscripts Utilized in Opcode Tables
- •B.3 One, Two, and THREE-Byte Opcode Maps
- •B.4.1 Opcode Look-up Examples Using Opcode Extensions
- •B.4.2 Opcode Extension Tables
- •B.5 Escape Opcode Instructions
- •B.5.1 Opcode Look-up Examples for Escape Instruction Opcodes
- •B.5.2 Escape Opcode Instruction Tables
- •B.5.2.1 Escape Opcodes with D8 as First Byte
- •B.5.2.2 Escape Opcodes with D9 as First Byte
- •B.5.2.3 Escape Opcodes with DA as First Byte
- •B.5.2.4 Escape Opcodes with DB as First Byte
- •B.5.2.5 Escape Opcodes with DC as First Byte
- •B.5.2.6 Escape Opcodes with DD as First Byte
- •B.5.2.7 Escape Opcodes with DE as First Byte
- •B.5.2.8 Escape Opcodes with DF As First Byte
INSTRUCTION SET REFERENCE
PMULLW/PMULLD - Multiply Packed Integers and Store Low Result
Opcode/ |
Op/ |
64/32 |
CPUID |
Description |
Instruction |
En |
-bit |
Feature |
|
|
|
Mode |
Flag |
|
66 0F D5 /r |
A |
V/V |
SSE2 |
Multiply the packed signed word |
PMULLW xmm1, xmm2/m128 |
|
|
|
integers in xmm1 and |
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|
|
|
xmm2/m128, and store the low |
|
|
|
|
16 bits of the results in xmm1 |
66 0F 38 40 /r |
A |
V/V |
SSE4_1 |
Multiply the packed dword |
PMULLD xmm1, xmm2/m128 |
|
|
|
signed integers in xmm1 and |
|
|
|
|
xmm2/m128 and store the low |
|
|
|
|
32 bits of each product in |
|
|
|
|
xmm1 |
VEX.NDS.128.66.0F.WIG D5 /r |
B |
V/V |
AVX |
Multiply the packed signed word |
VPMULLW xmm1, xmm2, |
|
|
|
integers in xmm2 and |
xmm3/m128 |
|
|
|
xmm3/m128, and store the low |
|
|
|
|
16 bits of the results in xmm1 |
VEX.NDS.128.66.0F38.WIG 40 /r |
B |
V/V |
AVX |
Multiply the packed dword |
VPMULLD xmm1, xmm2, |
|
|
|
signed integers in xmm2 and |
xmm3/m128 |
|
|
|
xmm3/m128 and store the low |
|
|
|
|
32 bits of each product in |
|
|
|
|
xmm1 |
VEX.NDS.256.66.0F.WIG D5 /r |
B |
V/V |
AVX2 |
Multiply the packed signed word |
VPMULLW ymm1, ymm2, |
|
|
|
integers in ymm2 and |
ymm3/m256 |
|
|
|
ymm3/m256, and store the low |
|
|
|
|
16 bits of the results in ymm1 |
VEX.NDS.256.66.0F38.WIG 40 /r |
B |
V/V |
AVX2 |
Multiply the packed dword |
VPMULLD ymm1, ymm2, |
|
|
|
signed integers in ymm2 and |
ymm3/m256 |
|
|
|
ymm3/m256 and store the low |
|
|
|
|
32 bits of each product in |
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|
|
ymm1 |
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|
5-138 |
Ref. # 319433-011 |
INSTRUCTION SET REFERENCE
Instruction Operand Encoding
Op/En |
Operand 1 |
Operand 2 |
Operand 3 |
Operand 4 |
A |
ModRM:reg (r, w) |
ModRM:r/m (r) |
NA |
NA |
B |
ModRM:reg (w) |
VEX.vvvv |
ModRM:r/m (r) |
NA |
|
|
|
|
|
Description
Performs a SIMD signed multiply of the packed signed word (dword) integers in the first source operand and the second source operand and stores the low 16(32) bits of each intermediate 32-bit(64-bit) result in the destination operand.
128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source operand is an XMM register or a 128-bit memory location. Bits (255:128) of the corresponding YMM destination register remain unchanged.
VEX.128 encoded version: The first source and destination operands are XMM registers. The second source operand is an XMM register or a 128-bit memory location. Bits (255:128) of the corresponding YMM register are zeroed.
VEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The first source and destination operands are YMM registers.
Operation
VPMULLD (VEX.256 encoded version)
Temp0[63:0] SRC1[31:0] * SRC2[31:0]
Temp1[63:0] SRC1[63:32] * SRC2[63:32]
Temp2[63:0] SRC1[95:64] * SRC2[95:64]
Temp3[63:0] SRC1[127:96] * SRC2[127:96]
Temp4[63:0] SRC1[159:128] * SRC2[159:128]
Temp5[63:0] SRC1[191:160] * SRC2[191:160]
Temp6[63:0] SRC1[223:192] * SRC2[223:192]
Temp7[63:0] SRC1[255:224] * SRC2[255:224]
DEST[31:0] Temp0[31:0]
DEST[63:32] Temp1[31:0]
DEST[95:64] Temp2[31:0]
DEST[127:96] Temp3[31:0]
DEST[159:128] Temp4[31:0]
DEST[191:160] Temp5[31:0]
DEST[223:192] Temp6[31:0]
DEST[255:224] Temp7[31:0]
VPMULLD (VEX.128 encoded version)
Ref. # 319433-011 |
5-139 |
INSTRUCTION SET REFERENCE
Temp0[63:0] SRC1[31:0] * SRC2[31:0]
Temp1[63:0] SRC1[63:32] * SRC2[63:32]
Temp2[63:0] SRC1[95:64] * SRC2[95:64]
Temp3[63:0] SRC1[127:96] * SRC2[127:96]
DEST[31:0] Temp0[31:0]
DEST[63:32] Temp1[31:0]
DEST[95:64] Temp2[31:0]
DEST[127:96] Temp3[31:0]
DEST[VLMAX:128] 0
PMULLD (128-bit Legacy SSE version)
Temp0[63:0] DEST[31:0] * SRC[31:0] Temp1[63:0] DEST[63:32] * SRC[63:32] Temp2[63:0] DEST[95:64] * SRC[95:64] Temp3[63:0] DEST[127:96] * SRC[127:96] DEST[31:0] Temp0[31:0]
DEST[63:32] Temp1[31:0]
DEST[95:64] Temp2[31:0]
DEST[127:96] Temp3[31:0]
DEST[VLMAX:128] (Unmodified)
VPMULLW (VEX.256 encoded version)
Temp0[31:0] SRC1[15:0] * SRC2[15:0] Temp1[31:0] SRC1[31:16] * SRC2[31:16] Temp2[31:0] SRC1[47:32] * SRC2[47:32] Temp3[31:0] SRC1[63:48] * SRC2[63:48] Temp4[31:0] SRC1[79:64] * SRC2[79:64] Temp5[31:0] SRC1[95:80] * SRC2[95:80] Temp6[31:0] SRC1[111:96] * SRC2[111:96] Temp7[31:0] SRC1[127:112] * SRC2[127:112] Temp8[31:0] SRC1[143:128] * SRC2[143:128] Temp9[31:0] SRC1[159:144] * SRC2[159:144] Temp10[31:0] SRC1[175:160] * SRC2[175:160] Temp11[31:0] SRC1[191:176] * SRC2[191:176] Temp12[31:0] SRC1[207:192] * SRC2[207:192] Temp13[31:0] SRC1[223:208] * SRC2[223:208] Temp14[31:0] SRC1[239:224] * SRC2[239:224] Temp15[31:0] SRC1[255:240] * SRC2[255:240] DEST[15:0] Temp0[15:0]
DEST[31:16] Temp1[15:0]
DEST[47:32] Temp2[15:0]
DEST[63:48] Temp3[15:0]
DEST[79:64] Temp4[15:0]
5-140 |
Ref. # 319433-011 |
INSTRUCTION SET REFERENCE
DEST[95:80] Temp5[15:0]
DEST[111:96] Temp6[15:0]
DEST[127:112] Temp7[15:0]
DEST[143:128] Temp8[15:0]
DEST[159:144] Temp9[15:0]
DEST[175:160] Temp10[15:0]
DEST[191:176] Temp11[15:0]
DEST[207:192] TEMP12[15:0]
DEST[223:208] Temp13[15:0]
DEST[239:224] Temp14[15:0]
DEST[255:240] Temp15[15:0]
VPMULLW (VEX.128 encoded version)
Temp0[31:0] SRC1[15:0] * SRC2[15:0]
Temp1[31:0] SRC1[31:16] * SRC2[31:16]
Temp2[31:0] SRC1[47:32] * SRC2[47:32]
Temp3[31:0] SRC1[63:48] * SRC2[63:48]
Temp4[31:0] SRC1[79:64] * SRC2[79:64]
Temp5[31:0] SRC1[95:80] * SRC2[95:80]
Temp6[31:0] SRC1[111:96] * SRC2[111:96]
Temp7[31:0] SRC1[127:112] * SRC2[127:112]
DEST[15:0] Temp0[15:0]
DEST[31:16] Temp1[15:0]
DEST[47:32] Temp2[15:0]
DEST[63:48] Temp3[15:0]
DEST[79:64] Temp4[15:0]
DEST[95:80] Temp5[15:0]
DEST[111:96] Temp6[15:0]
DEST[127:112] Temp7[15:0]
DEST[VLMAX:128] 0
PMULLW (128-bit Legacy SSE version)
Temp0[31:0] DEST[15:0] * SRC[15:0]
Temp1[31:0] DEST[31:16] * SRC[31:16]
Temp2[31:0] DEST[47:32] * SRC[47:32]
Temp3[31:0] DEST[63:48] * SRC[63:48]
Temp4[31:0] DEST[79:64] * SRC[79:64]
Temp5[31:0] DEST[95:80] * SRC[95:80]
Temp6[31:0] DEST[111:96] * SRC[111:96]
Temp7[31:0] DEST[127:112] * SRC[127:112]
DEST[15:0] Temp0[15:0]
DEST[31:16] Temp1[15:0]
DEST[47:32] Temp2[15:0]
Ref. # 319433-011 |
5-141 |
INSTRUCTION SET REFERENCE
DEST[63:48] Temp3[15:0]
DEST[79:64] Temp4[15:0]
DEST[95:80] Temp5[15:0]
DEST[111:96] Temp6[15:0]
DEST[127:112] Temp7[15:0]
DEST[127:96] Temp3[31:0];
DEST[VLMAX:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
(V)PMULLW __m128i _mm_mullo_epi16 ( __m128i a, __m128i b); (V)PMULLD __m128i _mm_mullo_epi32(__m128i a, __m128i b); VPMULLW __m256i _mm256_mullo_epi16 ( __m256i a, __m256i b); VPMULLD __m256i _mm256_mullo_epi32(__m256i a, __m256i b);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type 4
5-142 |
Ref. # 319433-011 |