- •Chapter 1 Intel® Advanced Vector Extensions
- •1.1 About This Document
- •1.2 Overview
- •1.3.2 Instruction Syntax Enhancements
- •1.3.3 VEX Prefix Instruction Encoding Support
- •1.4 Overview AVX2
- •1.5 Functional Overview
- •1.6 General Purpose Instruction Set Enhancements
- •2.1 Detection of PCLMULQDQ and AES Instructions
- •2.2 Detection of AVX and FMA Instructions
- •2.2.1 Detection of FMA
- •2.2.3 Detection of AVX2
- •2.3.1 FMA Instruction Operand Order and Arithmetic Behavior
- •2.4 Accessing YMM Registers
- •2.5 Memory alignment
- •2.7 Instruction Exception Specification
- •2.7.1 Exceptions Type 1 (Aligned memory reference)
- •2.7.2 Exceptions Type 2 (>=16 Byte Memory Reference, Unaligned)
- •2.7.3 Exceptions Type 3 (<16 Byte memory argument)
- •2.7.5 Exceptions Type 5 (<16 Byte mem arg and no FP exceptions)
- •2.7.7 Exceptions Type 7 (No FP exceptions, no memory arg)
- •2.7.8 Exceptions Type 8 (AVX and no memory argument)
- •2.8.1 Clearing Upper YMM State Between AVX and Legacy SSE Instructions
- •2.8.3 Unaligned Memory Access and Buffer Size Management
- •2.9 CPUID Instruction
- •3.1 YMM State, VEX Prefix and Supported Operating Modes
- •3.2 YMM State Management
- •3.2.1 Detection of YMM State Support
- •3.2.2 Enabling of YMM State
- •3.2.4 The Layout of XSAVE Area
- •3.2.5 XSAVE/XRSTOR Interaction with YMM State and MXCSR
- •3.2.6 Processor Extended State Save Optimization and XSAVEOPT
- •3.2.6.1 XSAVEOPT Usage Guidelines
- •3.3 Reset Behavior
- •3.4 Emulation
- •4.1 Instruction Formats
- •4.1.1 VEX and the LOCK prefix
- •4.1.2 VEX and the 66H, F2H, and F3H prefixes
- •4.1.3 VEX and the REX prefix
- •4.1.4 The VEX Prefix
- •4.1.4.1 VEX Byte 0, bits[7:0]
- •4.1.4.2 VEX Byte 1, bit [7] - ‘R’
- •4.1.5 Instruction Operand Encoding and VEX.vvvv, ModR/M
- •4.1.6 The Opcode Byte
- •4.1.7 The MODRM, SIB, and Displacement Bytes
- •4.1.8 The Third Source Operand (Immediate Byte)
- •4.1.9.1 Vector Length Transition and Programming Considerations
- •4.1.10 AVX Instruction Length
- •4.2 Vector SIB (VSIB) Memory Addressing
- •4.3 VEX Encoding Support for GPR Instructions
- •5.1 Interpreting InstructIon Reference Pages
- •5.1.1 Instruction Format
- •5.1.2 Opcode Column in the Instruction Summary Table
- •5.1.3 Instruction Column in the Instruction Summary Table
- •5.1.4 Operand Encoding column in the Instruction Summary Table
- •5.1.5 64/32 bit Mode Support column in the Instruction Summary Table
- •5.1.6 CPUID Support column in the Instruction Summary Table
- •5.2 Summary of Terms
- •5.3 Instruction SET Reference
- •MPSADBW - Multiple Sum of Absolute Differences
- •PALIGNR - Byte Align
- •PBLENDW - Blend Packed Words
- •PHADDW/PHADDD - Packed Horizontal Add
- •PHADDSW - Packed Horizontal Add with Saturation
- •PHSUBW/PHSUBD - Packed Horizontal Subtract
- •PHSUBSW - Packed Horizontal Subtract with Saturation
- •PMOVSX - Packed Move with Sign Extend
- •PMOVZX - Packed Move with Zero Extend
- •PMULDQ - Multiply Packed Doubleword Integers
- •PMULHRSW - Multiply Packed Unsigned Integers with Round and Scale
- •PMULHUW - Multiply Packed Unsigned Integers and Store High Result
- •PMULHW - Multiply Packed Integers and Store High Result
- •PMULLW/PMULLD - Multiply Packed Integers and Store Low Result
- •PMULUDQ - Multiply Packed Unsigned Doubleword Integers
- •POR - Bitwise Logical Or
- •PSADBW - Compute Sum of Absolute Differences
- •PSHUFB - Packed Shuffle Bytes
- •PSHUFD - Shuffle Packed Doublewords
- •PSHUFLW - Shuffle Packed Low Words
- •PSIGNB/PSIGNW/PSIGND - Packed SIGN
- •PSLLDQ - Byte Shift Left
- •PSLLW/PSLLD/PSLLQ - Bit Shift Left
- •PSRAW/PSRAD - Bit Shift Arithmetic Right
- •PSRLDQ - Byte Shift Right
- •PSRLW/PSRLD/PSRLQ - Shift Packed Data Right Logical
- •PSUBB/PSUBW/PSUBD/PSUBQ -Packed Integer Subtract
- •PSUBSB/PSUBSW -Subtract Packed Signed Integers with Signed Saturation
- •PSUBUSB/PSUBUSW -Subtract Packed Unsigned Integers with Unsigned Saturation
- •PXOR - Exclusive Or
- •VPBLENDD - Blend Packed Dwords
- •VPERMD - Full Doublewords Element Permutation
- •VPERMPD - Permute Double-Precision Floating-Point Elements
- •VPERMPS - Permute Single-Precision Floating-Point Elements
- •VPERMQ - Qwords Element Permutation
- •VPSLLVD/VPSLLVQ - Variable Bit Shift Left Logical
- •VPSRAVD - Variable Bit Shift Right Arithmetic
- •VPSRLVD/VPSRLVQ - Variable Bit Shift Right Logical
- •VGATHERDPD/VGATHERQPD - Gather Packed DP FP values Using Signed Dword/Qword Indices
- •VGATHERDPS/VGATHERQPS - Gather Packed SP FP values Using Signed Dword/Qword Indices
- •VPGATHERDD/VPGATHERQD - Gather Packed Dword values Using Signed Dword/Qword Indices
- •VPGATHERDQ/VPGATHERQQ - Gather Packed Qword values Using Signed Dword/Qword Indices
- •6.1 FMA InstructIon SET Reference
- •Chapter 7 Instruction Set Reference - VEX-Encoded GPR Instructions
- •7.1 Instruction Format
- •7.2 INSTRUCTION SET REFERENCE
- •BZHI - Zero High Bits Starting with Specified Bit Position
- •INVPCID - Invalidate Processor Context ID
- •Chapter 8 Post-32nm Processor Instructions
- •8.1 Overview
- •8.2 CPUID Detection of New Instructions
- •8.4 Vector Instruction Exception Specification
- •8.6 Using RDRAND Instruction and Intrinsic
- •8.7 Instruction Reference
- •A.1 AVX Instructions
- •A.2 Promoted Vector Integer Instructions in AVX2
- •B.1 Using Opcode Tables
- •B.2 Key to Abbreviations
- •B.2.1 Codes for Addressing Method
- •B.2.2 Codes for Operand Type
- •B.2.3 Register Codes
- •B.2.4 Opcode Look-up Examples for One, Two, and Three-Byte Opcodes
- •B.2.4.1 One-Byte Opcode Instructions
- •B.2.4.2 Two-Byte Opcode Instructions
- •B.2.4.3 Three-Byte Opcode Instructions
- •B.2.4.4 VEX Prefix Instructions
- •B.2.5 Superscripts Utilized in Opcode Tables
- •B.3 One, Two, and THREE-Byte Opcode Maps
- •B.4.1 Opcode Look-up Examples Using Opcode Extensions
- •B.4.2 Opcode Extension Tables
- •B.5 Escape Opcode Instructions
- •B.5.1 Opcode Look-up Examples for Escape Instruction Opcodes
- •B.5.2 Escape Opcode Instruction Tables
- •B.5.2.1 Escape Opcodes with D8 as First Byte
- •B.5.2.2 Escape Opcodes with D9 as First Byte
- •B.5.2.3 Escape Opcodes with DA as First Byte
- •B.5.2.4 Escape Opcodes with DB as First Byte
- •B.5.2.5 Escape Opcodes with DC as First Byte
- •B.5.2.6 Escape Opcodes with DD as First Byte
- •B.5.2.7 Escape Opcodes with DE as First Byte
- •B.5.2.8 Escape Opcodes with DF As First Byte
INSTRUCTION SET REFERENCE
PMULUDQ - Multiply Packed Unsigned Doubleword Integers
Opcode/ |
Op/ |
64/32 |
CPUID |
Description |
Instruction |
En |
-bit |
Feature |
|
|
|
Mode |
Flag |
|
66 0F F4 /r |
A |
V/V |
SSE4_1 |
Multiply packed unsigned double- |
PMULUDQ xmm1, xmm2/m128 |
|
|
|
word integers in xmm1 by |
|
|
|
|
packed unsigned doubleword |
|
|
|
|
integers in xmm2/m128, and |
|
|
|
|
store the quadword results in |
|
|
|
|
xmm1. |
VEX.NDS.128.66.0F.WIG F4 /r |
B |
V/V |
AVX |
Multiply packed unsigned double- |
VPMULUDQ xmm1, xmm2, |
|
|
|
word integers in xmm2 by |
xmm3/m128 |
|
|
|
packed unsigned doubleword |
|
|
|
|
integers in xmm3/m128, and |
|
|
|
|
store the quadword results in |
|
|
|
|
xmm1. |
VEX.NDS.256.66.0F.WIG F4 /r |
B |
V/V |
AVX2 |
Multiply packed unsigned double- |
VPMULUDQ ymm1, ymm2, |
|
|
|
word integers in ymm2 by |
ymm3/m256 |
|
|
|
packed unsigned doubleword |
|
|
|
|
integers in ymm3/m256, and |
|
|
|
|
store the quadword results in |
|
|
|
|
ymm1. |
|
|
|
|
|
Instruction Operand Encoding
Op/En |
Operand 1 |
Operand 2 |
Operand 3 |
Operand 4 |
A |
ModRM:reg (r, w) |
ModRM:r/m (r) |
NA |
NA |
B |
ModRM:reg (w) |
VEX.vvvv |
ModRM:r/m (r) |
NA |
|
|
|
|
|
Description
Multiplies packed unsigned doubleword integers in the first source operand by the packed unsigned doubleword integers in second source operand and stores packed unsigned quadword results in the destination operand.
128-bit Legacy SSE version: The second source operand is two packed unsigned doubleword integers stored in the first (low) and third doublewords of an XMM register or a 128-bit memory location. For 128-bit memory operands, 128 bits are fetched from memory, but only the first and third doublewords are used in the computation.The first source operand is two packed unsigned doubleword integers stored in the first and third doublewords of an XMM register. The destination contains two packed unsigned quadword integers stored in an XMM register. Bits (255:128) of the corresponding YMM destination register remain unchanged.
Ref. # 319433-011 |
5-143 |
INSTRUCTION SET REFERENCE
VEX.128 encoded version: The second source operand is two packed unsigned doubleword integers stored in the first (low) and third doublewords of an XMM register or a 128-bit memory location. For 128-bit memory operands, 128 bits are fetched from memory, but only the first and third doublewords are used in the computation.The first source operand is two packed unsigned doubleword integers stored in the first and third doublewords of an XMM register. The destination contains two packed unsigned quadword integers stored in an XMM register. Bits (255:128) of the corresponding YMM register are zeroed.
VEX.256 encoded version: The second source operand is four packed unsigned doubleword integers stored in the first (low), third, fifth and seventh doublewords of a YMM register or a 256-bit memory location. For 256-bit memory operands, 256 bits are fetched from memory, but only the first, third, fifth and seventh doublewords are used in the computation.The first source operand is four packed unsigned doubleword integers stored in the first, third, fifth and seventh doublewords of an YMM register. The destination contains four packed unaligned quadword integers stored in an YMM register.
Operation
VPMULUDQ (VEX.256 encoded version)
DEST[63:0] SRC1[31:0] * SRC2[31:0]
DEST[127:64] SRC1[95:64] * SRC2[95:64
DEST[191:128] SRC1[159:128] * SRC2[159:128]
DEST[255:192] SRC1[223:192] * SRC2[223:192]
VPMULUDQ (VEX.128 encoded version)
DEST[63:0] SRC1[31:0] * SRC2[31:0]
DEST[127:64] SRC1[95:64] * SRC2[95:64]
DEST[VLMAX:128] 0
PMULUDQ (128-bit Legacy SSE version)
DEST[63:0] DEST[31:0] * SRC[31:0]
DEST[127:64] DEST[95:64] * SRC[95:64]
DEST[VLMAX:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
(V)PMULUDQ __m128i _mm_mul_epu32( __m128i a, __m128i b);
VPMULUDQ __m256i _mm256_mul_epu32( __m256i a, __m256i b);
SIMD Floating-Point Exceptions
None
5-144 |
Ref. # 319433-011 |
INSTRUCTION SET REFERENCE
Other Exceptions
See Exceptions Type 4
Ref. # 319433-011 |
5-145 |
INSTRUCTION SET REFERENCE
POR - Bitwise Logical Or
Opcode/ |
Op/ |
64/32 |
CPUID |
Description |
Instruction |
En |
-bit |
Feature |
|
|
|
Mode |
Flag |
|
66 0F EB /r |
A |
V/V |
SSE2 |
Bitwise OR of xmm2/m128 |
POR xmm1, xmm2/m128 |
|
|
|
and xmm1. |
VEX.NDS.128.66.0F.WIG EB /r |
B |
V/V |
AVX |
Bitwise OR of xmm2/m128 |
VPOR xmm1, xmm2, xmm3/m128 |
|
|
|
and xmm3. |
VEX.NDS.256.66.0F.WIG EB /r |
B |
V/V |
AVX2 |
Bitwise OR of ymm2/m256 |
VPOR ymm1, ymm2, ymm3/m256 |
|
|
|
and ymm3. |
|
|
|
|
|
Instruction Operand Encoding
Op/En |
Operand 1 |
Operand 2 |
Operand 3 |
Operand 4 |
A |
ModRM:reg (r, w) |
ModRM:r/m (r) |
NA |
NA |
B |
ModRM:reg (w) |
VEX.vvvv |
ModRM:r/m (r) |
NA |
|
|
|
|
|
Description
Performs a bitwise logical OR operation on the second source operand and the first source operand and stores the result in the destination operand. Each bit of the result is set to 1 if either of the corresponding bits of the first and second operands are 1, otherwise it is set to 0.
128-bit Legacy SSE version: The second source operand is an XMM register or a 128bit memory location. The first source and destination operands can be XMM registers. Bits (255:128) of the corresponding YMM destination register remain unchanged.
VEX.128 encoded version: The second source operand is an XMM register or a 128bit memory location. The first source and destination operands can be XMM registers. Bits (255:128) of the corresponding YMM register are zeroed.
VEX.256 encoded version: The second source operand is an YMM register or a 256bit memory location. The first source and destination operands can be YMM registers.
Operation
VPOR (VEX.256 encoded version)
DEST SRC1 OR SRC2
VPOR (VEX.128 encoded version)
DEST[127:0] (SRC[127:0] OR SRC2[127:0])
DEST[VLMAX:128] 0
5-146 |
Ref. # 319433-011 |
INSTRUCTION SET REFERENCE
POR (128-bit Legacy SSE version)
DEST[127:0] (SRC[127:0] OR SRC2[127:0])
DEST[VLMAX:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
(V)POR __m128i _mm_or_si128 ( __m128i a, __m128i b) VPOR __m256i _mm256_or_si256 ( __m256i a, __m256i b)
SIMD Floating-Point Exceptions none
Other Exceptions
See Exceptions Type 4
Ref. # 319433-011 |
5-147 |