SYSTEM PROGRAMMING MODEL

CHAPTER 3

SYSTEM PROGRAMMING MODEL

This chapter describes the operating system programming considerations for AVX, F16C, AVX2 and FMA. The AES extension and PCLMULQDQ instruction follow the same system software requirements for XMM state support and SIMD floating-point exception support as SSE2, SSE3, SSSE3, SSE4 (see Chapter 12 of IA-32 Intel Architecture Software Developer’s Manual, Volumes 3A).

The AVX, F16C, AVX2 and FMA extensions operate on 256-bit YMM registers, and require operating system to supports processor extended state management using XSAVE/XRSTOR instructions. VAESDEC/VAESDECLAST/VAESENC/VAESENCLAST/VAESIMC/VAESKEYGENASSIST/VPCLMULQDQ follow the same system programming requirements as AVX and FMA instructions operating on YMM states.

The basic requirements for an operating system using XSAVE/XRSTOR to manage processor extended states for current and future Intel Architecture processors can be found in Chapter 12 of IA-32 Intel Architecture Software Developer’s Manual, Volumes 3A. This chapter covers additional requirements for OS to support YMM state.

3.1YMM STATE, VEX PREFIX AND SUPPORTED OPERATING MODES

AVX, F16C, AVX2 and FMA instructions operates on YMM states and requires VEX prefix encoding. SIMD instructions operating on XMM states (i.e. not accessing the upper 128 bits of YMM) generally do not use VEX prefix. Not all instructions that require VEX prefix encoding need YMM or XMM registers as operands.

For processors that support YMM states, the YMM state exists in all operating modes. However, the available interfaces to access YMM states may vary in different modes. The processor's support for instruction extensions that employ VEX prefix encoding is independent of the processor's support for YMM state.

Instructions requiring VEX prefix encoding generally are supported in 64-bit, 32-bit modes, and 16-bit protected mode. They are not supported in Real mode, Virtual8086 mode or entering into SMM mode.

Note that bits 255:128 of YMM register state are maintained across transitions into and out of these modes. Because, XSAVE/XRSTOR instruction can operate in all operating modes, it is possible that the processor's YMM register state can be modified by software in any operating mode by executing XRSTOR. The YMM registers can be updated by XRSTOR using the state information stored in the XSAVE/XRSTOR area residing in memory.