INSTRUCTION SET REFERENCE

PSADBW - Compute Sum of Absolute Differences

Instruction Operand Encoding

Description

Computes the absolute value of the difference of packed groups of 8 unsigned byte integers from the second source operand and from the first source operand. The first 8 differences are summed to produce an unsigned word integer that is stored in the low word of the destination; the second 8 differences are summed to produce an unsigned word in bits 79:64 of the destination. In case of VEX.256 encoded version, the third group of 8 differences are summed to produce an unsigned word in bits[143:128] of the destination register and the fourth group of 8 differences are

INSTRUCTION SET REFERENCE

summed to produce an unsigned word in bits[207:192] of the destination register. The remaining words of the destination are set to 0.

128-bit Legacy SSE version: The first source operand and destination register are XMM registers. The second source operand is an XMM register or a 128-bit memory location. Bits (255:128) of the corresponding YMM destination register remain unchanged.

VEX.128 encoded version: The first source operand and destination register are XMM registers. The second source operand is an XMM register or a 128-bit memory location. Bits (255:128) of the corresponding YMM register are zeroed.

VEX.256 encoded version: The first source operand and destination register are YMM registers. The second source operand is an YMM register or a 256-bit memory location.

Operation

VPSADBW (VEX.256 encoded version)

TEMP0  ABS(SRC1[7:0] - SRC2[7:0])

(* Repeat operation for bytes 2 through 30*) TEMP31  ABS(SRC1[255:248] - SRC2[255:248]) DEST[15:0] SUM(TEMP0:TEMP7)

DEST[63:16]  000000000000H DEST[79:64]  SUM(TEMP8:TEMP15) DEST[127:80]  00000000000H DEST[143:128] SUM(TEMP16:TEMP23) DEST[191:144]  000000000000H DEST[207:192]  SUM(TEMP24:TEMP31) DEST[223:208]  00000000000H

VPSADBW (VEX.128 encoded version)

TEMP0  ABS(SRC1[7:0] - SRC2[7:0])

(* Repeat operation for bytes 2 through 14 *) TEMP15  ABS(SRC1[127:120] - SRC2[127:120]) DEST[15:0] SUM(TEMP0:TEMP7)

DEST[63:16]  000000000000H DEST[79:64]  SUM(TEMP8:TEMP15) DEST[127:80]  00000000000H DEST[VLMAX:128]  0

PSADBW (128-bit Legacy SSE version)

TEMP0  ABS(DEST[7:0] - SRC[7:0])

(* Repeat operation for bytes 2 through 14 *) TEMP15  ABS(DEST[127:120] - SRC[127:120]) DEST[15:0] SUM(TEMP0:TEMP7)

DEST[63:16]  000000000000H

INSTRUCTION SET REFERENCE

DEST[79:64]  SUM(TEMP8:TEMP15)

DEST[127:80]  00000000000

DEST[VLMAX:128] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent

(V)PSADBW __m128i _mm_sad_epu8(__m128i a, __m128i b)

VPSADBW __m256i _mm256_sad_epu8( __m256i a, __m256i b)

SIMD Floating-Point Exceptions

None

Other Exceptions

See Exceptions Type 4

Description

PSHUFB performs in-place shuffles of bytes in the first source operand according to the shuffle control mask in the second source operand. The instruction permutes the data in the first source operand, leaving the shuffle mask unaffected. If the most significant bit (bit[7]) of each byte of the shuffle control mask is set, then constant zero is written in the result byte. Each byte in the shuffle control mask forms an index to permute the corresponding byte in the first source operand. The value of each index is the least significant 4 bits of the shuffle control byte. The first source and destination operands are XMM registers. The second source is either an XMM register or a 128-bit memory location.

128-bit Legacy SSE version: The first source and destination operands are the same. Bits (255:128) of the corresponding YMM destination register remain unchanged.

VEX.128 encoded version: Bits (255:128) of the destination YMM register are zeroed.

VEX.256 encoded version: Bits (255:128) of the destination YMM register stores the 16-byte shuffle result of the upper 16 bytes of the first source operand, using the upper 16-bytes of the second source operand as control mask. The value of each index is for the high 128-bit lane is the least significant 4 bits of the respective shuffle control byte. The index value selects a source data element within each 128-bit lane.

INSTRUCTION SET REFERENCE

Operation

VPSHUFB (VEX.256 encoded version) for i = 0 to 15 {

if (SRC2[(i * 8)+7] == 1 ) then DEST[(i*8)+7..(i*8)+0]  0; else

index[3..0]  SRC2[(i*8)+3 .. (i*8)+0]; DEST[(i*8)+7..(i*8)+0]  SRC1[(index*8+7)..(index*8+0)];

endif

if (SRC2[128 + (i * 8)+7] == 1 ) then DEST[128 + (i*8)+7..(i*8)+0]  0; else

index[3..0]  SRC2[128 + (i*8)+3 .. (i*8)+0];

DEST[128 + (i*8)+7..(i*8)+0]  SRC1[128 + (index*8+7)..(index*8+0)]; endif

}

VPSHUFB (VEX.128 encoded version) for i = 0 to 15 {

if (SRC2[(i * 8)+7] == 1 ) then DEST[(i*8)+7..(i*8)+0]  0; else

index[3..0]  SRC2[(i*8)+3 .. (i*8)+0]; DEST[(i*8)+7..(i*8)+0]  SRC1[(index*8+7)..(index*8+0)];

endif

}

DEST[VLMAX:128]  0

PSHUFB (128-bit Legacy SSE version) for i = 0 to 15 {

if (SRC[(i * 8)+7] == 1 ) then DEST[(i*8)+7..(i*8)+0]  0; else

index[3..0]  SRC[(i*8)+3 .. (i*8)+0]; DEST[(i*8)+7..(i*8)+0]  DEST[(index*8+7)..(index*8+0)];

endif

}

DEST[VLMAX:128] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent

(V)PSHUFB __m128i _mm_shuffle_epi8(__m128i a, __m128i b)

INSTRUCTION SET REFERENCE

VPSHUFB __m256i _mm256_shuffle_epi8(__m256i a, __m256i b)

SIMD Floating-Point Exceptions

None

Other Exceptions

See Exceptions Type 4