INSTRUCTION FORMAT

CHAPTER 4

INSTRUCTION FORMAT

AVX F16C, AVX2 and FMA instructions are encoded using a more efficient format than previous instruction extensions in the Intel 64 and IA-32 architecture. The improved encoding format uses a new prefix referred to as “VEX“. The VEX prefix may be two or three bytes long, depending on the instruction semantics. Despite the length of the VEX prefix, the instruction encoding format using VEX addresses two important issues: (a) there exists inefficiency in instruction encoding due to SIMD prefixes and some fields of the REX prefix, (b) Both SIMD prefixes and REX prefix increase in instruction byte-length. This chapter describes the instruction encoding format using VEX.

VEX-prefix encoding enables a subset of AVX2 instructions to support “vector SIM“ form of memory addressing. This is described in Section 4.2.

VEX-prefix encoding also enables some general purpose instructions to support three-operand syntax. This is described in Section 4.3.

4.1INSTRUCTION FORMATS

Legacy instruction set extensions in IA-32 architecture employs one or more “singlepurpose“ byte as an “escape opcode“, or required SIMD prefix (66H, F2H, F3H) to expand the processing capability of the instruction set. Intel 64 architecture uses the REX prefix to expand the encoding of register access in instruction operands. Both SIMD prefixes and REX prefix carry the side effect that they can cause the length of an instruction to increase significantly. Legacy Intel 64 and IA-32 instruction set are limited to supporting instruction syntax of only two operands that can be encoded to access registers (and only one can access a memory address).

Instruction encoding using VEX prefix provides several advantages:

•Instruction syntax support for three operands and up-to four operands when necessary. For example, the third source register used by VBLENDVPD is encoded using bits 7:4 of the immediate byte.

•Encoding support for vector length of 128 bits (using XMM registers) and 256 bits (using YMM registers)

•Encoding support for instruction syntax of non-destructive source operands.

•Elimination of escape opcode byte (0FH), SIMD prefix byte (66H, F2H, F3H) via a compact bit field representation within the VEX prefix.

•Elimination of the need to use REX prefix to encode the extended half of generalpurpose register sets (R8-R15) for direct register access, memory addressing, or accessing XMM8-XMM15 (including YMM8-YMM15).