APPLICATION PROGRAMMING MODEL
2.7.5Exceptions Type 5 (<16 Byte mem arg and no FP exceptions)
Table 2-14. Type 5 Class Exception Conditions
Exception |
Real |
Virtual80x86 |
Protectedand Compatibility |
64-bit |
Cause of Exception |
|
|
|
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||
|
|
|
|
|
|
Invalid Opcode, #UD |
X |
X |
|
|
VEX prefix |
|
|
|
|
|
|
|
|
|
X |
X |
VEX prefix: |
|
|
|
|
|
If XFEATURE_ENABLED_MASK[2:1] != ‘11b’. |
|
|
|
|
|
If CR4.OSXSAVE[bit 18]=0. |
|
|
|
|
|
|
|
X |
X |
X |
X |
Legacy SSE instruction: |
|
|
|
|
|
If CR0.EM[bit 2] = 1. |
|
|
|
|
|
If CR4.OSFXSR[bit 9] = 0. |
|
|
|
|
|
|
|
X |
X |
X |
X |
If preceded by a LOCK prefix (F0H) |
|
|
|
|
|
|
|
|
|
X |
X |
If any REX, F2, F3, or 66 prefixes precede a |
|
|
|
|
|
VEX prefix |
|
|
|
|
|
|
|
X |
X |
X |
X |
If any corresponding CPUID feature flag is ‘0’ |
|
|
|
|
|
|
Device Not Available, |
X |
X |
X |
X |
If CR0.TS[bit 3]=1 |
#NM |
|
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|
|
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|
Stack, SS(0) |
|
|
X |
|
For an illegal address in the SS segment |
|
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|
X |
If a memory address referencing the SS seg- |
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|
ment is in a non-canonical form |
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|
General Protection, |
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|
X |
|
For an illegal memory operand effective |
#GP(0) |
|
|
|
|
address in the CS, DS, ES, FS or GS segments. |
|
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|
|
|
|
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|
X |
If the memory address is in a non-canonical |
|
|
|
|
|
form. |
|
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|
|
|
|
X |
X |
|
|
If any part of the operand lies outside the |
|
|
|
|
|
effective address space from 0 to FFFFH |
|
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|
Page Fault |
|
X |
X |
X |
For a page fault |
#PF(fault-code) |
|
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|
|
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|
Alignment Check |
|
X |
X |
X |
If alignment checking is enabled and an |
#AC(0) |
|
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|
unaligned memory reference is made while |
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|
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|
the current privilege level is 3. |
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|
Ref. # 319433-011 |
2-25 |
APPLICATION PROGRAMMING MODEL
2.7.6Exceptions Type 6 (VEX-Encoded Instructions Without Legacy SSE Analogues)
Note: At present, the AVX instructions in this category do not generate floating-point exceptions.
Table 2-15. Type 6 Class Exception Conditions
Exception |
Real |
Virtual80x86 |
Protectedand Compatibility |
64-bit |
Cause of Exception |
|
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||
|
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|
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|
|
Invalid Opcode, #UD |
X |
X |
|
|
VEX prefix |
|
|
|
|
|
|
|
|
|
X |
X |
If XFEATURE_ENABLED_MASK[2:1] != ‘11b’. |
|
|
|
|
|
If CR4.OSXSAVE[bit 18]=0. |
|
|
|
|
|
|
|
|
|
X |
X |
If preceded by a LOCK prefix (F0H) |
|
|
|
|
|
|
|
|
|
X |
X |
If any REX, F2, F3, or 66 prefixes precede a |
|
|
|
|
|
VEX prefix |
|
|
|
|
|
|
|
|
|
X |
X |
If any corresponding CPUID feature flag is ‘0’ |
|
|
|
|
|
|
Device Not Available, |
|
|
X |
X |
If CR0.TS[bit 3]=1 |
#NM |
|
|
|
|
|
|
|
|
|
|
|
Stack, SS(0) |
|
|
X |
|
For an illegal address in the SS segment |
|
|
|
|
|
|
|
|
|
|
X |
If a memory address referencing the SS seg- |
|
|
|
|
|
ment is in a non-canonical form |
|
|
|
|
|
|
General Protection, |
|
|
X |
|
For an illegal memory operand effective |
#GP(0) |
|
|
|
|
address in the CS, DS, ES, FS or GS segments. |
|
|
|
|
|
|
|
|
|
|
X |
If the memory address is in a non-canonical |
|
|
|
|
|
form. |
|
|
|
|
|
|
Page Fault |
|
|
X |
X |
For a page fault |
#PF(fault-code) |
|
|
|
|
|
|
|
|
|
|
|
Alignment Check |
|
|
X |
X |
For 4 or 8 byte memory references if align- |
#AC(0) |
|
|
|
|
ment checking is enabled and an unaligned |
|
|
|
|
|
memory reference is made while the current |
|
|
|
|
|
privilege level is 3. |
|
|
|
|
|
|
2-26 |
Ref. # 319433-011 |
APPLICATION PROGRAMMING MODEL
2.7.7Exceptions Type 7 (No FP exceptions, no memory arg)
Table 2-16. Type 7 Class Exception Conditions
Exception |
Real |
Virtual80x86 |
Protectedand Compatibility |
64-bit |
Cause of Exception |
|
|
|
|
||
|
|
|
|
|
|
Invalid Opcode, #UD |
X |
X |
|
|
VEX prefix |
|
|
|
|
|
|
|
|
|
X |
X |
VEX prefix: |
|
|
|
|
|
If XFEATURE_ENABLED_MASK[2:1] != ‘11b’. |
|
|
|
|
|
If CR4.OSXSAVE[bit 18]=0. |
|
|
|
|
|
|
|
X |
X |
X |
X |
Legacy SSE instruction: |
|
|
|
|
|
If CR0.EM[bit 2] = 1. |
|
|
|
|
|
If CR4.OSFXSR[bit 9] = 0. |
|
|
|
|
|
|
|
X |
X |
X |
X |
If preceded by a LOCK prefix (F0H) |
|
|
|
|
|
|
|
|
|
X |
X |
If any REX, F2, F3, or 66 prefixes precede a |
|
|
|
|
|
VEX prefix |
|
|
|
|
|
|
|
X |
X |
X |
X |
If any corresponding CPUID feature flag is ‘0’ |
|
|
|
|
|
|
Device Not Available, |
|
|
X |
X |
If CR0.TS[bit 3]=1 |
#NM |
|
|
|
|
|
|
|
|
|
|
|
2.7.8Exceptions Type 8 (AVX and no memory argument)
Table 2-17. Type 8 Class Exception Conditions
Exception
Invalid Opcode, #UD
Device Not Available, #NM
Real |
Virtual 80x86 |
Protected and Compatibility |
64-bit |
X |
X |
|
|
|
|
X |
X |
X |
X |
X |
X |
|
|
X |
X |
|
|
|
|
Cause of Exception
Always in Real or Virtual 80x86 mode
If XFEATURE_ENABLED_MASK[2:1] != ‘11b’. If CR4.OSXSAVE[bit 18]=0.
If CPUID.01H.ECX.AVX[bit 28]=0. If VEX.vvvv != 1111B.
If proceeded by a LOCK prefix (F0H) If CR0.TS[bit 3]=1.
Ref. # 319433-011 |
2-27 |
APPLICATION PROGRAMMING MODEL
2.7.9Exception Type 11 (VEX-only, mem arg no AC, floating-point exceptions)
Table 2-18. Type 11 Class Exception Conditions
Exception |
Real |
Virtual80x86 |
Protectedand Compatibility |
64-bit |
Cause of Exception |
|
|
|
|
||
|
|
|
|
|
|
Invalid Opcode, #UD |
X |
X |
|
|
VEX prefix |
|
|
|
|
|
|
|
|
|
X |
X |
VEX prefix: |
|
|
|
|
|
If XFEATURE_ENABLED_MASK[2:1] != ‘11b’. |
|
|
|
|
|
If CR4.OSXSAVE[bit 18]=0. |
|
|
|
|
|
|
|
X |
X |
X |
X |
If preceded by a LOCK prefix (F0H) |
|
|
|
|
|
|
|
|
|
X |
X |
If any REX, F2, F3, or 66 prefixes precede a |
|
|
|
|
|
VEX prefix |
|
|
|
|
|
|
|
X |
X |
X |
X |
If any corresponding CPUID feature flag is ‘0’ |
|
|
|
|
|
|
Device Not Available, |
X |
X |
X |
X |
If CR0.TS[bit 3]=1 |
#NM |
|
|
|
|
|
|
|
|
|
|
|
Stack, SS(0) |
|
|
X |
|
For an illegal address in the SS segment |
|
|
|
|
|
|
|
|
|
|
X |
If a memory address referencing the SS seg- |
|
|
|
|
|
ment is in a non-canonical form |
|
|
|
|
|
|
General Protection, |
|
|
X |
|
For an illegal memory operand effective |
#GP(0) |
|
|
|
|
address in the CS, DS, ES, FS or GS segments. |
|
|
|
|
|
|
|
|
|
|
X |
If the memory address is in a non-canonical |
|
|
|
|
|
form. |
|
|
|
|
|
|
|
X |
X |
|
|
If any part of the operand lies outside the |
|
|
|
|
|
effective address space from 0 to FFFFH |
|
|
|
|
|
|
Page Fault |
|
X |
X |
X |
For a page fault |
#PF(fault-code) |
|
|
|
|
|
|
|
|
|
|
|
SIMD Floating-Point |
X |
X |
X |
X |
If an unmasked SIMD floating-point exception |
Exception, #XM |
|
|
|
|
and CR4.OSXMMEXCPT[bit 10] = 1 |
|
|
|
|
|
|
2-28 |
Ref. # 319433-011 |
APPLICATION PROGRAMMING MODEL
2.7.10Exception Type 12 (VEX-only, VSIB mem arg, no AC, no floating-point exceptions)
Table 2-19. Type 12 Class Exception Conditions
Exception |
Real |
Virtual80x86 |
Protectedand Compatibility |
64-bit |
Cause of Exception |
|
|
|
|
||
|
|
|
|
|
|
Invalid Opcode, #UD |
X |
X |
|
|
VEX prefix |
|
|
|
|
|
|
|
|
|
X |
X |
VEX prefix: |
|
|
|
|
|
If XFEATURE_ENABLED_MASK[2:1] != ‘11b’. |
|
|
|
|
|
If CR4.OSXSAVE[bit 18]=0. |
|
|
|
|
|
|
|
X |
X |
X |
X |
If preceded by a LOCK prefix (F0H) |
|
|
|
|
|
|
|
|
|
X |
X |
If any REX, F2, F3, or 66 prefixes precede a |
|
|
|
|
|
VEX prefix |
|
|
|
|
|
|
|
X |
X |
X |
NA |
If address size attribute is 16 bit |
|
|
|
|
|
|
|
X |
X |
X |
X |
If ModR/M.mod = ‘11b’ |
|
|
|
|
|
|
|
X |
X |
X |
X |
If ModR/M.rm != ‘100b’ |
|
|
|
|
|
|
|
X |
X |
X |
X |
If any corresponding CPUID feature flag is ‘0’ |
|
|
|
|
|
|
|
X |
X |
X |
X |
If any vector register is used more than once |
|
|
|
|
|
between the destination register, mask regis- |
|
|
|
|
|
ter and the index register in VSIB addressing. |
|
|
|
|
|
|
Device Not Available, |
X |
X |
X |
X |
If CR0.TS[bit 3]=1 |
#NM |
|
|
|
|
|
|
|
|
|
|
|
Stack, SS(0) |
|
|
X |
|
For an illegal address in the SS segment |
|
|
|
|
|
|
|
|
|
|
X |
If a memory address referencing the SS seg- |
|
|
|
|
|
ment is in a non-canonical form |
|
|
|
|
|
|
General Protection, |
|
|
X |
|
For an illegal memory operand effective |
#GP(0) |
|
|
|
|
address in the CS, DS, ES, FS or GS segments. |
|
|
|
|
|
|
|
|
|
|
X |
If the memory address is in a non-canonical |
|
|
|
|
|
form. |
|
|
|
|
|
|
|
X |
X |
|
|
If any part of the operand lies outside the |
|
|
|
|
|
effective address space from 0 to FFFFH |
|
|
|
|
|
|
Page Fault #PF(fault- |
|
X |
X |
X |
For a page fault |
code) |
|
|
|
|
|
|
|
|
|
|
|
Ref. # 319433-011 |
2-29 |
APPLICATION PROGRAMMING MODEL
2.7.11Exception Conditions for VEX-Encoded GPR Instructions
The exception conditions applicable to VEX-encoded GPR instruction differs from those of legacy GPR instructions. Table 2-20 groups instructions listed in Chapter 7 and lists details of the exception conditions for VEX-encoded GRP instructions in Table 2-22 for those instructions which have a default operand size of 32 bits and 16bit operand size is not encodable. Table 2-21 lists exception conditions for those instructions that support operation on 16-bit operands.
Table 2-20. Exception Groupings for Instructions Listed in Chapter 7
Exception Class |
Instruction |
|
|
See Table 2-21 |
LZCNT, TZCNT |
|
|
See Table 2-22 |
ANDN, BLSI, BLSMSK, BLSR, BZHI, MULX, PDEP, PEXT, RORX, SARX, SHLX, |
|
SHRX |
|
|
(*) - Additional exception restrictions are present - see the Instruction description for details
Table 2-21. Exception Definition for LZCNT and TZCNT
Exception |
Real |
Virtual80x86 |
Protectedand Compatibility |
64-bit |
Cause of Exception |
|
|
|
|
||
|
|
|
|
|
|
Stack, SS(0) |
X |
X |
X |
|
For an illegal address in the SS segment |
|
|
|
|
|
|
|
|
|
|
X |
If a memory address referencing the SS seg- |
|
|
|
|
|
ment is in a non-canonical form |
|
|
|
|
|
|
General Protection, |
|
|
X |
|
For an illegal memory operand effective |
#GP(0) |
|
|
|
|
address in the CS, DS, ES, FS or GS segments. |
|
|
|
|
|
If the DS, ES, FS, or GS register is used to |
|
|
|
|
|
access memory and it contains a null segment |
|
|
|
|
|
selector. |
|
|
|
|
|
|
|
|
|
|
X |
If the memory address is in a non-canonical |
|
|
|
|
|
form. |
|
|
|
|
|
|
|
X |
X |
|
|
If any part of the operand lies outside the |
|
|
|
|
|
effective address space from 0 to FFFFH |
|
|
|
|
|
|
Page Fault #PF(fault- |
|
X |
X |
X |
For a page fault |
code) |
|
|
|
|
|
|
|
|
|
|
|
Alignment Check |
|
X |
X |
X |
If alignment checking is enabled and an |
#AC(0) |
|
|
|
|
unaligned memory reference is made while the |
|
|
|
|
|
current privilege level is 3. |
|
|
|
|
|
|
2-30 |
Ref. # 319433-011 |
APPLICATION PROGRAMMING MODEL
Table 2-22. Exception Definition (VEX-Encoded GPR Instructions)
Exception |
Real |
Virtual80x86 |
Protectedand Compatibility |
64-bit |
Cause of Exception |
|
|
|
|
||
|
|
|
|
|
|
Invalid Opcode, #UD |
X |
X |
X |
X |
If BMI1/BMI2 CPUID feature flag is ‘0’ |
|
|
|
|
|
|
|
X |
X |
|
|
If a VEX prefix is present |
|
|
|
|
|
|
|
|
|
X |
X |
If any REX, F2, F3, or 66 prefixes precede a |
|
|
|
|
|
VEX prefix |
|
|
|
|
|
|
Stack, SS(0) |
X |
X |
X |
|
For an illegal address in the SS segment |
|
|
|
|
|
|
|
|
|
|
X |
If a memory address referencing the SS seg- |
|
|
|
|
|
ment is in a non-canonical form |
|
|
|
|
|
|
General Protection, |
|
|
X |
|
For an illegal memory operand effective |
#GP(0) |
|
|
|
|
address in the CS, DS, ES, FS or GS segments. |
|
|
|
|
|
If the DS, ES, FS, or GS register is used to |
|
|
|
|
|
access memory and it contains a null segment |
|
|
|
|
|
selector. |
|
|
|
|
|
|
|
|
|
|
X |
If the memory address is in a non-canonical |
|
|
|
|
|
form. |
|
|
|
|
|
|
|
X |
X |
|
|
If any part of the operand lies outside the |
|
|
|
|
|
effective address space from 0 to FFFFH |
|
|
|
|
|
|
Page Fault #PF(fault- |
|
X |
X |
X |
For a page fault |
code) |
|
|
|
|
|
|
|
|
|
|
|
Alignment Check |
|
X |
X |
X |
If alignment checking is enabled and an |
#AC(0) |
|
|
|
|
unaligned memory reference is made while the |
|
|
|
|
|
current privilege level is 3. |
|
|
|
|
|
|
2.8PROGRAMMING CONSIDERATIONS WITH 128-BIT SIMD INSTRUCTIONS
VEX-encoded SIMD instructions generally operate on the 256-bit YMM register state. In contrast, non-VEX encoded instructions (e.g from SSE to AES) operating on XMM registers only access the lower 128-bit of YMM registers. Processors supporting both 256-bit VEX-encoded instructions and legacy 128-bit SIMD instructions have internal state to manage the upper and lower halves of the YMM register states. Functionally, VEX-encoded SIMD instructions can be intermixed with legacy SSE instructions (non- VEX-encoded SIMD instructions operating on XMM registers). However, there is a
Ref. # 319433-011 |
2-31 |