INSTRUCTION SET REFERENCE - VEX-ENCODED GPR INSTRUCTIONS

CHAPTER 7 INSTRUCTION SET REFERENCE - VEX-ENCODED GPR INSTRUCTIONS

This chapter describes the various general-purpose instructions, the majority of which are encoded using VEX prefix.

7.1INSTRUCTION FORMAT

The format used for describing each instruction as in the example below is described in chapter 5.

ANDN - Logical And Not

Instruction Operand Encoding

7.2INSTRUCTION SET REFERENCE

INSTRUCTION SET REFERENCE - VEX-ENCODED GPR INSTRUCTIONS

ANDN — Logical AND NOT

Instruction Operand Encoding

Description

Performs a bitwise logical AND of inverted second operand (the first source operand) with the third source operand (the second source operand). The result is stored in the first operand (destination operand).

This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.

Operation

DEST ← (NOT SRC1) bitwiseAND SRC2;

SF ← DEST[OperandSize -1];

ZF ← (DEST = 0);

Flags Affected

SF and ZF are updated based on result. OF and CF flags are cleared. AF and PF flags are undefined.

Intel C/C++ Compiler Intrinsic Equivalent

Auto-generated from high-level language.

SIMD Floating-Point Exceptions

None

INSTRUCTION SET REFERENCE - VEX-ENCODED GPR INSTRUCTIONS

Other Exceptions

See Table 2-22.

INSTRUCTION SET REFERENCE - VEX-ENCODED GPR INSTRUCTIONS

BEXTR — Bit Field Extract

NOTES:

1.ModRM:r/m is used to encode the first source operand (second operand) and VEX.vvvv encodes the second source operand (third operand).

Instruction Operand Encoding

Description

Extracts contiguous bits from the first source operand (the second operand) using an index value and length value specified in the second source operand (the third operand). Bit 7:0 of the first source operand specifies the starting bit position of bit extraction. A START value exceeding the operand size will not extract any bits from the second source operand. Bit 15:8 of the second source operand specifies the maximum number of bits (LENGTH) beginning at the START position to extract. Only bit positions up to (OperandSize -1) of the first source operand are extracted. The extracted bits are written to the destination register, starting from the least significant bit. All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed. The destination register is cleared if no bits are extracted.

This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.

Operation

START ← SRC2[7:0];

LEN ← SRC2[15:8];

TEMP ← ZERO_EXTEND_TO_512 (SRC1 );

DEST ← ZERO_EXTEND(TEMP[START+LEN -1: START]);

ZF ← (DEST = 0);

INSTRUCTION SET REFERENCE - VEX-ENCODED GPR INSTRUCTIONS

Flags Affected

ZF is updated based on the result. AF, SF, and PF are undefined. All other flags are cleared.

Intel C/C++ Compiler Intrinsic Equivalent

BEXTRunsigned __int32 _bextr_u32(unsigned __int32 src, unsigned __int32 start. unsigned __int32 len);

BEXTRunsigned __int64 _bextr_u64(unsigned __int64 src, unsigned __int32 start. unsigned __int32 len);

SIMD Floating-Point Exceptions

None

Other Exceptions

See Table 2-22.

INSTRUCTION SET REFERENCE - VEX-ENCODED GPR INSTRUCTIONS

BLSI — Extract Lowest Set Isolated Bit

Instruction Operand Encoding

Description

Extracts the lowest set bit from the source operand and set the corresponding bit in the destination register. All other bits in the destination operand are zeroed. If no bits are set in the source operand, BLSI sets all the bits in the destination to 0 and sets ZF and CF.

This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.

Operation

temp ← (-SRC) bitwiseAND (SRC); SF ← temp[OperandSize -1];

ZF ← (temp = 0); IF SRC = 0

CF ← 0; ELSE

CF ← 1;

FI

DEST ← temp;

Flags Affected

ZF and SF are updated based on the result. CF is set if the source is not zero. OF flags are cleared. AF and PF flags are undefined.

INSTRUCTION SET REFERENCE - VEX-ENCODED GPR INSTRUCTIONS

Intel C/C++ Compiler Intrinsic Equivalent

BLSI unsigned __int32 _blsi_u32(unsigned __int32 src);

BLSI unsigned __int64 _blsi_u64(unsigned __int64 src);

SIMD Floating-Point Exceptions

None

Other Exceptions

See Table 2-22.

INSTRUCTION SET REFERENCE - VEX-ENCODED GPR INSTRUCTIONS

BLSMSK — Get Mask Up to Lowest Set Bit

Instruction Operand Encoding

Description

Sets all the lower bits of the destination operand to “1” up to and including lowest set bit (=1) in the source operand. If source operand is zero, BLSMSK sets all bits of the destination operand to 1 and also sets CF to 1.

This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.

Operation

temp ← (SRC-1) XOR (SRC) ; SF ← temp[OperandSize -1]; ZF ← 0;

IF SRC = 0 CF ← 1;

ELSE

CF ← 0;

FI

DEST ← temp;

Flags Affected

SF is updated based on the result. CF is set if the source if zero. ZF and OF flags are cleared. AF and PF flag are undefined.

INSTRUCTION SET REFERENCE - VEX-ENCODED GPR INSTRUCTIONS

Intel C/C++ Compiler Intrinsic Equivalent

BLSMSK unsigned __int32 _blsmsk_u32(unsigned __int32 src);

BLSMSK unsigned __int64 _blsmsk_u64(unsigned __int64 src);

SIMD Floating-Point Exceptions

None

Other Exceptions

See Table 2-22.

INSTRUCTION SET REFERENCE - VEX-ENCODED GPR INSTRUCTIONS

BLSRReset Lowest Set Bit

Instruction Operand Encoding

Description

Copies all bits from the source operand to the destination operand and resets (=0) the bit position in the destination operand that corresponds to the lowest set bit of the source operand. If the source operand is zero BLSR sets CF.

This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.

Operation

temp ← (SRC-1) bitwiseAND ( SRC ); SF ← temp[OperandSize -1];

ZF ← (temp = 0); IF SRC = 0

CF ← 1; ELSE

CF ← 0;

FI

DEST ← temp;

Flags Affected

ZF and SF flags are updated based on the result. CF is set if the source is zero. OF flag is cleared. AF and PF flags are undefined.

INSTRUCTION SET REFERENCE - VEX-ENCODED GPR INSTRUCTIONS

Intel C/C++ Compiler Intrinsic Equivalent

BLSR unsigned __int32 _blsr_u32(unsigned __int32 src);

BLSR unsigned __int64 _blsr_u64(unsigned __int64 src);

SIMD Floating-Point Exceptions

None

Other Exceptions

See Table 2-22.