TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720

Floating-Point Digital Signal Processors

www.ti.com

SPRS370C–SEPTEMBER 2006–REVISED OCTOBER 2007

5 Application Example

Figure 5-1 illustrates a high-level block diagram of the device and other devices to which it may typically connect. See Section 1.2 for an overview of each major block.

 

 

DSP

 

 

 

 

 

 

 

 

 

Audio Zone 1

CODEC, DIR,

 

 

 

McASP0

ADC, DAC, DSD,

 

 

256K

SPI or I2C

 

 

 

 

Network

 

Controller

Bytes

SPI1

 

C67x+

 

Audio Zone 2

 

 

RAM

 

Control (optional)

 

DSP Core

 

 

 

 

 

 

 

I2C0

 

 

 

 

 

 

 

 

 

Program

Memory

ROM

McASP1

 

Network

 

 

384K

 

 

Audio Zone 3

CODEC, DIR,

 

 

Bytes

McASP2

ADC, DAC, DSD,

 

 

 

Cache

 

 

SPIO

 

 

 

 

 

 

I2C1

 

 

 

Crossbar Switch

RTI

 

 

Digital Out,

 

 

 

 

 

TDM Port

 

 

 

 

 

 

EMIF

dMAX

UHPI

PLL

OSC

 

 

 

 

 

 

 

 

6 Independent Audio

 

 

 

 

 

 

Zones (3 TX + 3 RX)

 

 

 

 

 

 

16 Serial Data Pins

ASYNC

High Speed

 

DSP Control

 

FLASH

 

 

 

 

Parallel Data

 

SPI or I2C

 

133 MHz

 

Host

 

 

 

Microprocessor

 

 

 

SDRAM

 

 

 

 

 

 

 

 

A.UHPI is only available on the C6727B. McASP2 is not available on the C6722B and C6720.

Figure 5-1. TMS320C672x Audio DSP System Diagram

106

Application Example

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TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720

Floating-Point Digital Signal Processors

www.ti.com

SPRS370C–SEPTEMBER 2006–REVISED OCTOBER 2007

6 Revision History

This revision history highlights the technical changes made to the SPRS370B device-specific data sheet to make it an SPRS370C revision.

Scope: Updated Table 4-10, EMIF Asynchronous Interface Switching Characteristics.

ADDS/CHANGES/DELETES

Table 4-10, EMIF Asynchronous Interface Switching Characteristics:

tc(EM_CLK): Added MIN value for 133-MHz EMIF frequency

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Revision History

107

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