TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720

Floating-Point Digital Signal Processors

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SPRS370C–SEPTEMBER 2006–REVISED OCTOBER 2007

4.18 Phase-Locked Loop (PLL)

4.18.1 PLL Device-Specific Information

The C672x DSP generates the high-frequency internal clocks it requires through an on-chip PLL.

The input to the PLL is either from the on-chip oscillator (OSCIN pin) or from an external clock on the CLKIN pin. The PLL outputs four clocks that have programmable divider options. Figure 4-43 illustrates the PLL Topology.

The PLL is disabled by default after a device reset. It must be configured by software according to the allowable operating conditions listed in Table 4-42 before enabling the DSP to run from the PLL by setting PLLEN = 1.

Figure 4-43. PLL Topology

(1)Some values for the D0 divider produce results outside of this range and should not be selected.

(2)In general, selecting the PLL output clock rate closest to the maximum frequency will decrease clock jitter.

CAUTION

SYSCLK1, SYSCLK2, SYSCLK3 must be configured as aligned by setting ALNCTL[2:0] to '1'; and the PLLCMD.GOSET bit must be written every time the dividers D1, D2, and D3 are changed in order to make sure the change takes effect and preserves alignment.

CAUTION

When changing the PLL parameters which affect the SYSCLK1, SYSCLK2, SYSCLK3 dividers, the bridge BR2 in Figure 2-4 must be reset by the CFGBRIDGE register. See Table 2-7.

The PLL is an analog circuit and is sensitive to power supply noise. Therefore it has a dedicated 3.3-V power pin (PLLHV) that should be connected to DVDD at the board level through an external filter, as illustrated in Figure 4-44.

EMI Filter: TDK ACF451832−333, −223, −153, or −103,

Panasonic EXCCET103U, or Equivalent

Figure 4-44. PLL Power Supply Filter