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SPRS370C–SEPTEMBER 2006–REVISED OCTOBER 2007

4.12 Universal Host-Port Interface (UHPI) [C6727B Only]

4.12.1 UHPI Device-Specific Information

The C672x DSP includes a flexible universal host-port interface (UHPI) with more options than the host-port interface on the C671x DSP.

The UHPI on the C672x DSP supports three major operating modes listed in Table 4-11.

Table 4-11. UHPI Major Modes on C672x

In all modes, the UHPI uses three select inputs (UHPI_HCS, UHPI_HDS[2:1]) which are combined internally to produce the internal strobe signal HSTROBE. The HSTROBE strobe signal is used in the UHPI to capture incoming address and control signals on its falling edge and write data on its rising edge. The UHPI_HCS signal also gates the deassertion of the UHPI_HRDY signal externally.

UHPI_HCS

UHPI_HRDY

Internal HRDY

Figure 4-14. UHPI Strobe and Ready Interaction

The two HPI control pins UHPI_HCNTL[1:0] determine the type of access that the host will perform. Note that only two of the four access types are supported in Non-Multiplexed Host Address/Data Fullword Mode.

Table 4-12. HPI Access Types Selected by UHPI_HCNTL[1:0]

CAUTION

When performing a set of HPID with autoincrementing address accesses (UHPI_HCNTL[1:0] = '01'), the set must begin and end at a word-aligned address. In addition, all four of the UHPI_HBE[3:0] must be enabled on every access in the set.

CAUTION

The encoding of UHPI_CNTL[1:0] on the C672x DSP is different from HCNTL[1:0] on the C671x DSP. Modes 01 and 10 are swapped.

TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720

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SPRS370C–SEPTEMBER 2006–REVISED OCTOBER 2007

Figure 4-15 illustrates the Multiplexed Host Address/Data Half-Word Mode hookup between the C672x DSP and an external host microcontroller. In this mode, each 32-bit HPI access is broken up into two halves. The UHPI_HD[16]/HHWIL pin functions as UHPI_HHWIL which must be '0' during the first half of access and '1' during the second half.

CAUTION

Unless configured as general-purpose I/O in the UHPI module, UHPI_HD[31:17] and UHPI_HD[16]/HHWIL will be driven as outputs along with UHPI_HD[15:0] when the HPI is read, even though only the lower half-word is used to transfer data. This can be especially problematic for the UHPI_HD[16]/HHWIL pin which should be used as an input in this mode. Therefore, be sure to configure the upper half of the UHPI_HD bus as general-purpose I/O pins. Furthermore, be sure to program the UHPI_HD[16] function as a general-purpose input to avoid a drive conflict with the external host MCU.

In this mode, as well as the Multiplexed Host Address/Data Fullword mode, the UHPI can be made more secure by restricting the upper 16 bits of the DSP addresses it can access to what is set in CFGHPIAMSB and CFGHPIAUMB registers. (See Table 4-15 and Table 4-16).

The host is responsible for configuring the internal HPIA register whether or not it is being overridden by the device configuration registers CFGHPIAMSB and CFGHPIAUMB.

After the HPIA register has been set, either a single or a group of autoincrementing accesses to HPID may be performed.

The UHPI_HRDY adds wait states to extend the host MCU access until the C672x DSP has completed the desired operation.

The HINT signal is available for the DSP to interrupt the host MCU. The UHPI also includes an interrupt to the DSP core from the host as part of the HPIC register.

A.May be used as EM_D[31:16]

B.Optional for hosts supporting multiplexed address and data. Pull up if not used. Low when address is on the bus.

C.DSP byte enables UHPI_HBE[3:2] are not required in this mode.

D.Two host address lines or host GPIO if address lines are not available.

E.A[1], assuming this address increments from 0 to 1 between two successive 16-bit accesses.

F.Byte Enables (active during reads and writes). Some processors support a byte-enable mode on their write-enable pins.

G.Only required if needed for strobe timing. Not required if CS meets strobe timing requirements. Tie UHPI_HDS[2] and UHPI_HDS[1] opposite. For more information, see Figure 4-14.

Figure 4-15. UHPI Multiplexed Host Address/Data Half-Word Mode

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Figure 4-16 illustrates the Multiplexed Host Address/Data Fullword Mode hookup between the C672x DSP and an external host microcontroller. In this mode, all 32 bits of UHPI_HD[31:0] are used and the host can access HPIA, HPID, and HPIC in a single bus cycle.

A.May be used as EM_D[31:16]

B.Optional for hosts supporting multiplexed address and data. Pull up if not used. Low when address is on the bus.

C.Two host address lines or host GPIO if address lines are not available.

D.Byte Enables (active during reads and writes). Some processors support a byte-enable mode on their write enable pins.

E.Only required if needed for strobe timing. Not required if CS meets strobe timing requirements.

Figure 4-16. UHPI Multiplexed Host Address/Data Fullword Mode

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SPRS370C–SEPTEMBER 2006–REVISED OCTOBER 2007

Figure 4-17 illustrates the Non-Multiplexed Host Address/Data Fullword mode of the UHPI. In this mode, the UHPI behaves almost like an asynchronous SRAM except it asserts the UHPI_HRDY signal. This mode allows the host to randomly access a 64K-byte page in the C672x address space. The upper 32 bits of the C672x address are set by the DSP (only) through the CFGHPIAMSB and CFGHPIAUMB registers (see Table 4-15 and Table 4-16).

A.Two host address lines or host GPIO if address lines are not available.

B.Not used in this mode.

C.Byte Enables (active during reads and writes). Some processors support a byte-enable mode on their write enable pins.

D.Only required if needed for strobe timing. Not required if CS meets strobe timing requirements.

Figure 4-17. UHPI Non-Multiplexed Host Address/Data Fullword Mode

CAUTION

The EMIF data bus and UHPI HA inputs share the EM_D[31:16]/UHPI_HA[15:0] pins. When using Non-Multiplexed mode, make sure the EMIF does not drive EM_D[31:16]; otherwise, a drive conflict with the external host MCU may result. Normally, the EMIF will begin to drive the EM_D[31:16] lines immediately after it completes the SDRAM initialization sequence, which occurs automatically after RESET is released. To avoid a drive conflict then, the boot software must set CFGHPI.NMUX to '1' before the EMIF drives EM_D[31:16]. Setting CFGHPI.NMUX to '1' forces these pins to be input pins.