TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720
Floating-Point Digital Signal Processors
www.ti.com
SPRS370C–SEPTEMBER 2006–REVISED OCTOBER 2007
4.8 Reset
A hardware reset (RESET) is required to place the DSP into a known good state out of power-up. The RESET signal can be asserted (pulled low) prior to ramping the core and I/O voltages or after the core and I/O voltages have reached their proper operating conditions. As a best practice, RESET should be held low during power-up. Prior to deasserting RESET (low-to-high transition), the core and I/O voltages should be at their proper operating conditions.
4.8.1Reset Electrical Data/Timing
Table 4-1 assumes testing over recommended operating conditions.
Table 4-1. Reset Timing Requirements
NO. |
|
|
MIN |
MAX UNIT |
1 |
tw(RSTL) |
Pulse width, RESET low |
100 |
ns |
2 |
tsu(BPV-RSTH) |
Setup time, boot pins valid before RESET high |
20 |
ns |
3 |
th(RSTH-BPV) |
Hold time, boot pins valid after RESET high |
20 |
ns |
38 |
Peripheral and Electrical Specifications |
Submit Documentation Feedback |