nRF24L01+ Product Specification
5.5Crystal specifications
Symbol |
Parameter (condition) |
Notes |
Min. |
Typ. |
Max. |
Units |
Fxo |
Crystal Frequency |
|
|
16 |
|
MHz |
F |
Tolerance |
a b |
|
|
±60 |
ppm |
|
|
|
|
|
|
|
C0 |
Equivalent parallel capacitance |
|
|
1.5 |
7.0 |
pF |
Ls |
Equivalent serial inductance |
c |
|
30 |
|
mH |
|
|
|
|
|
|
|
CL |
Load capacitance |
|
8 |
12 |
16 |
pF |
ESR |
Equivalent Series Resistance |
|
|
|
100 |
Ω |
a.Frequency accuracy including; tolerance at 25ºC, temperature drift, aging and crystal loading.
b.Frequency regulations in certain regions set tighter requirements for frequency tolerance (For example, Japan and South Korea specify max. +/- 50ppm).
c.Startup time from power down to standby mode is dependant on the Ls parameter. See Table 16. on page 24 for details.
Table 11. Crystal specifications
The crystal oscillator startup time is proportional to the crystal equivalent inductance. The trend in crystal design is to reduce the physical outline. An effect of a small outline is an increase in equivalent serial inductance Ls, which gives a longer startup time. The maximum crystal oscillator startup time, Tpd2stby = 1.5 ms, is set using a crystal with equivalent serial inductance of maximum 30mH.
An application specific worst case startup time can be calculated as :
Tpd2stby= Ls/30mH *1.5ms if Ls exceeds 30mH.
Note: In some crystal datasheets Ls is called L1 or Lm and Cs is called C1 or Cm.
Co
ESR Cs Ls
Figure 3. Equivalent crystal components
Revision 1.0 |
Page 19 of 78 |
nRF24L01+ Product Specification
5.6DC characteristics
|
Symbol |
|
Parameter (condition) |
Notes |
|
Min. |
|
Typ. |
Max. |
|
Units |
||
|
|
VIH |
HIGH level input voltage |
|
|
0.7VDD |
|
|
5.25a |
|
V |
||
|
|
VIL |
LOW level input voltage |
|
|
|
VSS |
|
|
0.3VDD |
|
V |
|
|
|
a. If the input signal >3.6V, the VDD of the nRF24L01+ must be between 2.7V and 3.3V (3.0V±10%) |
|
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|
Table 12. Digital input pin |
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|
Symbol |
|
Parameter (condition) |
Notes |
|
Min. |
|
Typ. |
Max. |
|
Units |
||
|
|
VOH |
HIGH level output voltage (IOH=-0.25mA) |
|
|
VDD -0.3 |
|
|
VDD |
|
V |
||
|
|
VOL |
LOW level output voltage (IOL=0.25mA) |
|
|
|
|
|
|
0.3 |
|
V |
|
|
|
|
|
Table 13. Digital output pin |
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|||
5.7 |
Power on reset |
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|
Symbol |
|
Parameter (condition) |
|
Notes |
Min. |
|
Typ. |
Max. |
|
Units |
|
|
|
TPUP |
|
Power ramp up time |
|
a |
|
|
|
100 |
|
ms |
|
|
|
TPOR |
|
Power on reset |
|
b |
1 |
|
|
100 |
|
ms |
|
a. From 0V to 1.9V.
b. Measured from when the VDD reaches 1.9V to when the reset finishes.
Table 14. Power on reset
Revision 1.0 |
Page 20 of 78 |