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GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION

E.4.2.3 Condition Codes, Exception Flags, and Response for Masked and Unmasked Numeric Exceptions

In the following, the masked response is what the processor provides when a masked exception is raised by an SSE/SSE2/SSE3 numeric instruction. The same response is provided by the float- ing-point emulator for SSE/SSE2/SSE3 numeric instructions, when certain components of the quadruple input operands generate exceptions that are masked (the emulator also generates the correct answer, as specified by IEEE Standard 754 wherever applicable, in the case when no floating-point exception occurs). The unmasked response is what the emulator provides to the user handler for those components of the packed operands of SSE/SSE2/SSE3 instructions that raise unmasked exceptions. Note that for pre-computation exceptions (floating-point faults), no result is provided to the user handler. For post-computation exceptions (floating-point traps), a result is provided to the user handler, as specified below.

In the following tables, the result is denoted by 'res', with the understanding that for the actual instruction, the destination coincides with the first source operand (except for COMISS, UCOMISS, COMISD, and UCOMISD, whose destination is the EFLAGS register).

	Table E-13.	#I - Invalid Operations
				Unmasked
Instruction	Condition		Masked Response	Response and
				Exception Code
ADDPS	src1 or src21 = SNaN		Refer to Table E-1 for	src1, src2
ADDPD			NaN operands, #IA = 1	unchanged; #IA = 1
ADDSS
ADDSD
HADDPS
HADDPD
ADDSUBPS (the	src1 = +Inf, src2 = -Inf or		res1 = QNaN Indefinite,
addition	src1 = -Inf, src2 = +Inf		#IA = 1
component)
ADDSUBPD (the
addition
component)
SUBPS	src1 or src2 = SNaN		Refer to Table E-1 for NaN	src1, src2
SUBPD			operands, #IA = 1	unchanged; #IA = 1
SUBSS
SUBSD
HSUBPS
HSUBPD
ADDSUBPS (the	src1 = +Inf, src2 = +Inf or		res = QNaN Indefinite,
subtraction	src1 = -Inf, src2 = -Inf		#IA = 1
component)
ADDSUBPD (the
subtraction
component)

E-12 Vol. 1

GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION

Table E-13. #I - Invalid Operations (Contd.)

			Unmasked
Instruction	Condition	Masked Response	Response and
			Exception Code
MULPS	src1 or src2 = SNaN	Refer to Table E-1 for	src1, src2
MULPD		NaN operands, #IA = 1	unchanged;
			#IA = 1
MULSS	src1 = ±Inf, src2 = ±0 or	res = QNaN Indefinite,	#IA = 1
MULSS	src1 = ±Inf, src2 = ±0 or	res = QNaN Indefinite,
MULSD	src1 = ±0, src2 = ±Inf	#IA = 1

DIVPS	src1 or src2 = SNaN	Refer to Table E-1 for	src1, src2
DIVPD		NaN operands, #IA = 1	unchanged;
			#IA = 1
DIVSS	src1 = ±Inf, src2 = ±Inf or	res = QNaN Indefinite,	#IA = 1
DIVSS	src1 = ±Inf, src2 = ±Inf or	res = QNaN Indefinite,
DIVSD	src1 = ±0, src2 = ±0	#IA = 1

SQRTPS	src = SNaN	Refer to Table E-10 for	src unchanged,
SQRTPD		NaN operands, #IA = 1	#IA = 1
SQRTSS
SQRTSS	src < 0	res = QNaN Indefinite,
SQRTSD	src < 0	res = QNaN Indefinite,
SQRTSD	(note that -0 < 0 is false)	#IA = 1
	(note that -0 < 0 is false)	#IA = 1

MAXPS	src1 = NaN or src2 = NaN	res = src2, #IA = 1	src1, src2
MAXSS			unchanged; #IA = 1
MAXPD
MAXSD
MINPS	src1 = NaN or src2 = NaN	res = src2, #IA = 1	src1, src2
MINSS			unchanged; #IA = 1
MINPD
MINSD
CMPPS.LT	src1 = NaN or src2 = NaN	Refer to Table E-4 and	src1, src2
CMPPS.LE		Table E-5 for NaN	unchanged; #IA = 1
CMPPS.NLT		operands; #IA = 1
CMPPS.NLE
CMPSS.LT
CMPSS.LE
CMPSS.NLT
CMPSS.NLE
CMPPD.LT
CMPPD.LE
CMPPD.NLT
CMPPD.NLE
CMPSD.LT
CMPSD.LE
CMPSD.NLT
CMPSD.NLE
COMISS	src1 = NaN or src2 = NaN	Refer to Table E-6 for NaN	src1, src2, EFLAGS
COMISD		operands	unchanged; #IA = 1
UCOMISS	src1 = SNaN or src2 = SNaN	Refer to Table E-7 for NaN	src1, src2, EFLAGS
UCOMISD		operands	unchanged; #IA = 1

Vol. 1 E-13

GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION

Table E-13. #I - Invalid Operations (Contd.)

			Unmasked
Instruction	Condition	Masked Response	Response and
			Exception Code
CVTPS2PI	src = NaN, ±Inf, or	res = Integer Indefinite,	src unchanged,
CVTSS2SI	\|(src)rnd \| > 7FFFFFFFH and	#IA = 1	#IA = 1
CVTPD2PI	(src)rnd ≠80000000H
CVTSD2SI	See Note2 for information
CVTPS2DQ	See Note2 for information
CVTPD2DQ	on rnd.
CVTTPS2PI	src = NaN, ±Inf, or	res = Integer Indefinite,	src unchanged,
CVTTSS2SI	\|(src)rz \| > 7FFFFFFFH and	#IA = 1	#IA = 1
CVTTPD2PI	(src)rz ≠80000000H
CVTTSD2SI	See Note2 for information
CVTTPS2DQ	See Note2 for information
CVTTPD2DQ	on rz.
CVTPS2PD	src = NAN	Refer to Table E-11 for	src unchanged,
CVTSS2SD		NaN operands	#IA = 1
CVTPD2PS	src = NAN	Refer to Table E-12 for	src unchanged,
CVTSD2SS		NaN operands	#IA = 1

NOTES:

1.For Tables E-13 to E-18:

-src denotes the single source operand of a unary operation.

-src1, src2 denote the first and second source operand of a binary operation.

-res denotes the numerical result of an operation.

2.rnd signifies the user rounding mode from MXCSR, and rz signifies the rounding mode toward zero. (truncate), when rounding a floating-point value to an integer. For more information, refer to Table 4-8.

3.For NAN encodings, see Table 4-3.

Table E-14. #Z - Divide-by-Zero

			Unmasked
Instruction	Condition	Masked Response	Response and
			Exception Code
DIVPS	src1 = finite non-zero (normal, or	res = ±Inf,	src1, src2
DIVSS	denormal)	#ZE = 1	unchanged;
DIVPD	src2 = ±0		#ZE = 1
DIVPS

E-14 Vol. 1

GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION

Table E-15. #D - Denormal Operand

			Unmasked Response and
Instruction	Condition	Masked Response	Exception Code

ADDPS	src1 = denormal1 or	res = Result rounded to the	src1, src2 unchanged;
ADDPD	src2 = denormal (and	destination precision and	#DE = 1
ADDSUBPS	the DAZ bit in MXCSR	using the bounded
ADDSUBPD	is 0)	exponent, but only if no	Note that SQRT,
HADDPS		unmasked post-	CVTPS2PD, CVTSS2SD,
HADDPD		computation exception	CVTPD2PS, CVTSD2SS
SUBPS		occurs.	have only 1 src.
SUBPD
HSUBPS
HSUBPD
MULPS
MULPD
DIVPS
DIVPD
SQRTPS
SQRTPD
MAXPS
MAXPD
MINPS
MINPD
CMPPS
CMPPD
ADDSS
ADDSD
SUBSS
SUBSD
MULSS
MULSD
DIVSS
DIVSD
SQRTSS
SQRTSD
MAXSS
MAXSD
MINSS
MINSD
CMPSS
CMPSD
COMISS
COMISD
UCOMISS
UCOMISD
CVTPS2PD
CVTSS2SD
CVTPD2PS
CVTSD2SS

NOTE:

1. For denormal encodings, see Section 4.8.3.2, “Normalized and Denormalized Finite Numbers”.

Vol. 1 E-15

GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION

Table E-16. #O - Numeric Overflow

			Unmasked Response and
Instruction	Condition	Masked Response	Exception Code

ADDPS	Rounded result >	Rounding	Sign	Result & Status Flags	res = (result calculated with
ADDSUBPS	largest single	Rounding	Sign	Result & Status Flags	unbounded exponent and
ADDSUBPS	largest single				unbounded exponent and
HADDPS	precision finite	To		#OE = 1, #PE = 1	rounded to the destination
SUBPS	normal value	nearest	+	res = + ∞	precision) / 2192
HSUBPS			-	res = –∞	•	#OE = 1
MULPS					• #PE = 1 if the result is
MULPS		Toward		#OE = 1, #PE = 1
DIVPS		Toward		#OE = 1, #PE = 1
ADDSS		–∞	+	res = 1.11…1 * 2127		inexact
SUBSS			-	res = –∞
MULSS
MULSS		Toward		#OE = 1, #PE = 1
DIVSS		Toward		#OE = 1, #PE = 1
DIVSS		+ ∞	+	res = + ∞
CVTPD2PS		+ ∞	+	res = + ∞
CVTPD2PS			-	res = -1.11…1 * 2127
CVTSD2SS			-	res = -1.11…1 * 2127
		Toward		#OE = 1, #PE = 1
		0	+	res = 1.11…1 * 2127
			-	res = -1.11…1 * 2127
ADDPD	Rounded result >	Rounding	Sign	Result & Status Flags	res = (result calculated with
ADDSUBPD	largest double	Rounding	Sign	Result & Status Flags	unbounded exponent and
ADDSUBPD	largest double				unbounded exponent and
HADDPD	precision finite	To		#OE = 1, #PE = 1	rounded to the destination
SUBPD	normal value	nearest	+	res = + ∞	precision) / 21536
HSUBPD			-	res = –∞	•	#OE = 1
MULPD					• #PE = 1 if the result is
MULPD		Toward		#OE = 1, #PE = 1
DIVPD
DIVPD						inexact
ADDSD		–∞	+	res = 1.11…1 * 21023		inexact
SUBSD			-	res = –∞
MULSD
MULSD		Toward		#OE = 1, #PE = 1
DIVSD		Toward		#OE = 1, #PE = 1
DIVSD		+ ∞	+	res = + ∞
		+ ∞	+	res = + ∞
			-	res = -1.11…1 * 21023
		Toward		#OE = 1, #PE = 1
		0	+	res = 1.11…1 * 21023
			-	res = -1.11…1 * 21023

E-16 Vol. 1

GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION

Table E-17. #U - Numeric Underflow

				Unmasked Response
Instruction	Condition	Masked Response		and Exception Code

ADDPS	Result calculated with	res = ±0, denormal, or	res = (result calculated with
ADDSUBPS	unbounded exponent and	normal	unbounded exponent and
HADDPS	rounded to the destination		rounded to the destination
SUBPS	precision < smallest single	#UE = 1 and #PE = 1,	precision) * 2192
HSUBPS	precision finite normal	but only if the result is	•	#UE = 1
MULPS	value.	inexact	• #PE = 1 if the result is
DIVPS			• #PE = 1 if the result is
DIVPS				inexact
ADDSS				inexact
ADDSS
SUBSS
MULSS
DIVSS
CVTPD2PS
CVTSD2SS

ADDPD	Result calculated with	res = ±0, denormal or	res = (result calculated with
ADDSUBPD	unbounded exponent and	normal	unbounded exponent and
HADDPD	rounded to the destination		rounded to the destination
SUBPD	precision < smallest double	#UE = 1 and #PE = 1,	precision) * 21536
HSUBPD	precision finite normal	but only if the result is	•	#UE = 1
MULPD	value.	inexact	• #PE = 1 if the result is
DIVPD			• #PE = 1 if the result is
DIVPD				inexact
ADDSD				inexact
ADDSD
SUBSD
MULSD
DIVSD

Vol. 1 E-17

GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION

Table E-18. #P - Inexact Result (Precision)

			Unmasked Response and Exception
Instruction	Condition	Masked Response	Code

ADDPS	The result is not	res = Result rounded	Only if no underflow/overflow condition
ADDPD	exactly	to the destination	occurred, or if the corresponding
ADDSUBPS	representable in the	precision and using	exceptions are masked:
ADDSUBPD	destination format.	the bounded	• Set #OE if masked overflow and set
HADDPS		exponent, but only if	result as described above for masked
HADDPD		no unmasked	overflow.
SUBPS		underflow or overflow	• Set #UE if masked underflow and set
SUBPD		conditions occur (this	• Set #UE if masked underflow and set
SUBPD		conditions occur (this	result as described above for masked
HSUBPS		exception can occur	result as described above for masked
HSUBPS		exception can occur	underflow.
HSUBPD		in the presence of a	underflow.
HSUBPD		in the presence of a
MULPS		masked underflow or	If neither underflow nor overflow, res
MULPD		overflow); #PE = 1.	equals the result rounded to the
DIVPS			destination precision and using the
DIVPD			bounded exponent set #PE = 1.
SQRTPS
SQRTPD
CVTDQ2PS
CVTPI2PS
CVTPS2PI
CVTPS2DQ
CVTPD2PI
CVTPD2DQ
CVTPD2PS
CVTTPS2PI
CVTTPD2PI
CVTTPD2DQ
CVTTPS2DQ
ADDSS
ADDSD
SUBSS
SUBSD
MULSS
MULSD
DIVSS
DIVSD
SQRTSS
SQRTSD
CVTSI2SS
CVTSS2SI
CVTSD2SI
CVTSD2SS
CVTTSS2SI
CVTTSD2SI

E-18 Vol. 1

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