PROGRAMMING WITH STREAMING SIMD EXTENSIONS 3 (SSE3)

fourth by subtracting the fourth element of the second operand from the third element of the second operand.

•HSUBPS OperandA, OperandB

—OperandA (128 bits, four data elements): 3a, 2a, 1a, 0a

—OperandB (128 bits, four data elements): 3b, 2b, 1b, 0b

—Result (Stored in OperandA): 2b-3b, 0b-1b, 2a-3a, 0a-1a

The HADDPD instruction performs a double-precision addition on contiguous data elements. The first data element of the result is obtained by adding the first and second elements of the first operand; the second element by adding the first and second elements of the second operand.

•HADDPD OperandA, OperandB

—OperandA (128 bits, two data elements): 1a, 0a

—OperandB (128 bits, two data elements): 1b, 0b

—Result (Stored in OperandA): 1b+0b, 1a+0a

The HSUBPD instruction performs a double-precision subtraction on contiguous data elements. The first data element of the result is obtained by subtracting the second element of the first operand from the first element of the first operand; the second element by subtracting the second element of the second operand from the first element of the second operand.

•HSUBPD OperandA OperandB

—OperandA (128 bits, two data elements): 1a, 0a

—OperandB (128 bits, two data elements): 1b, 0b

—Result (Stored in OperandA): 0b-1b, 0a-1a

12.3.6Two Thread Synchronization Instructions

The MONITOR instruction sets up an address range that is used to monitor write-back-stores.

MWAIT enables a logical processor to enter into an optimized state while waiting for a write- back-store to the address range set up by MONITOR. MONITOR and MWAIT require the use of general purpose registers for its input. The registers used by MONITOR and MWAIT must be initialized properly; register content is not modified by these instructions.

12.4SSE3 EXCEPTIONS

SSE3 instructions can generate the same type of memory-access and non-numeric exceptions as other IA-32 architecture instructions. Existing exception handlers generally handle these exceptions without code modification.

FISTTP can generate floating-point exceptions. Some SSE3 instructions can also generate SIMD floating-point exceptions.

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