1. Match words from the text with their definitions.

1. To obtain A. Extremely unusual or uncommon.

2. Adjacent B. To increase in size, number, volume, degree,

etc

3. To expand C. To become the owner of, esp. by means of effort

or planning.

4. Rare D. Very close; touching or almost touching.

2. Identify whether the following statements are true or false. Use the model:

1. Student A: Some secondary caches can be expanded, some cannot. — Student B: Yes, that is true.

S. A: The control unit interprets the instruction and looks for the necessary data in RAM first. — S. B: No, that is false. It interprets the instruction and looks for the necessary data in the cache memory first. If the data is there, it processed; otherwise the control unit looks for the data in RAM.

1. The cache memory was introduced to increase speed of instruction

execution.

2 . The analysis of programs showed that all the memory cells are frequently

accessed.

3 . After the program had been executed, some of the variables are held in

the cache memory.

4. A cache memory controller retrieves instructions from ROM.

5. The capacity of built-in cache is between 8 and 32K, depending on the microprocessor.

6. Associative cache is generally slower than direct mapped cache.

3. Join the sentences with the proper variant in the right column.

1. Write back cache holds off ....a) although rare and expensive, writing to the hard disk

2. A more sophisticated cache b) ranges in size from 64K to 1M. memory keeps

3. The built-in cache memory c) an alternative architecture to direct

mapped memory.

4. Associative cache describes d) until there is a lull in CPU activity.

5. Cache SRAM at speeds up e) a count of number of accesses made to 8ns has recently become to each variable, available

6. The capacity of external cache f) is located inside the CPU.

4. Answer the following questions

1. What was the reason of the cache memory introduction?

2. What are the functions of the control unit in case of cache memory?

3. What can a more sophisticated cache memory do?

4. What is called a cache memory controller?

1. What types of cache memory help to speed up the computer's performance?

2. What cache holds off writing to the hard disk until there is a lull in CPU activity?

3. What cache describes an alternative architecture to direct mapped memory?

5. What cache SRAM is generally used for system boards?

5. Read the text

In order to make room for the new entry on a cache miss, the cache generally has to evict one of the existing entries. The heuristic that it uses to choose the entry to evict is called the replacement policy. The fundamental problem with any replacement policy is that it must predict which existing cache entry is least likely to be used in the future. Predicting the future i_s difficult, especially for hardware caches which use simple rules amenable to implementation in circuitry, so there are a variety of replacement policies to choose from and no perfect way to decide among them. One popular replacement policy, LRU, replaces the least recently used entry.

When data is written to the cache, it must at some point be written to main memory as well. The timing of this write is controlled by what is known as the write policy. In a write-through cache, every write to the cache causes a write to main memory. Alternatively, in a write-back 01 copy-back cache, writes are not immediately mirrored to memory. Instead, the cache tracks which locations have been written over (these locations are marked dirty). The data in these locations is written back to main memory when that data is evicted from the cache. For this reason, a miss in a write-back cache will often require two memory accesses to service: one to read the new location from memory and the other to write the dirty location to memory. This is also called batch mode.

There are intermediate policies as well. The cache may be write-through, but the writes may be held in a store data queue temporarily, usually so that multiple stores can be processed together (which can reduce bus turnarounds and so improve bus utilization).

The data in main memory being cached may be changed by other entities, in which case the copy in the cache may become out-of-date 01 stale. Alternatively, when the CPU updates the data in the cache, copies of data in other caches will become stale. Communication protocols between the cache managers which keep the data consistent are known as cache coherenct protocols.