Serial Peripheral Interface (SPI) Port —Slave Timing

Table 24 and Figure 16 describe SPI port slave operations.

Table 24. Serial Peripheral Interface (SPI) Port—Slave Timing

Parameter				Min		Max	Unit
Timing Requirements
tSPICHS	Serial Clock High Period			2tSCLK			ns
tSPICLS	Serial Clock Low Period			2tSCLK			ns
tSPICLK	Serial Clock Period			4tSCLK			ns
tHDS	Last SPICLK Edge to SPISS Not Asserted			2tSCLK			ns
tSPITDS	Sequential Transfer Delay			2tSCLK			ns
tSDSCI	SPISS Assertion to First SCK Edge			2tSCLK			ns
tSSPID	Data Input Valid to SCK Edge (Data Input Setup)			1.6			ns
tHSPID	SCK Sampling Edge to Data Input Invalid			1.6			ns
Switching Characteristics
tDSOE	SPISS Assertion to Data Out Active			0.0		6.0	ns
tDSDHI	SPISS Deassertion to Data High Impedance			0.0		6.5	ns
tDDSPID	SCK Edge to Data Out Valid (Data Out Delay)			0.0		7.0	ns
tHDSPID	SCK Edge to Data Out Invalid (Data Out Hold)			0.0		6.5	ns
	SPISSx
	(INPUT)
		tSPICHS	tSPICLS	tSPICLK	tHDS	tSPITDS
	SCK
	(CPOL = 0)
	(INPUT)
	tSDSCI	tSPICLS	tSPICHS
	SCK
	(CPOL = 1)
	(INPUT)
	tDSOE	tDDSPID	tHDSPID	tDDSPID	tDSDHI
	tDSOE		tHDSPID	tDDSPID	tDSDHI
	MISO		MSB		LSB
	(OUTPUT)		MSB		LSB
	(OUTPUT)
CPHA = 1	tSSPID		tHSPID	tSSPID	tHSPID
				tSSPID

	MOSI	MSB		LSB
	(INPUT)	VALID		VALID
	tDSOE	tDDSPID			tDSDHI
		tDDSPID
	MISO	MSB		LSB
	(OUTPUT)	MSB		LSB
	(OUTPUT)
CPHA = 0			tSSPID	tHSPID
			tSSPID	tHSPID
	MOSI	MSB		LSB
	(INPUT)	VALID		VALID

Figure 16. Serial Peripheral Interface (SPI) Port—Slave Timing

REV. A

–33–

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