a |
DSP MicrocomputerSHARC |
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ADSP-21160M |
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SUMMARY |
KEY FEATURES |
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High-Performance 32-Bit DSP—Applications in Audio, |
80 MHz (12.5 ns) Core Instruction Rate |
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Medical, Military, Graphics, Imaging, and |
Single-Cycle Instruction Execution, Including SIMD |
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Communication |
Operations in Both Computational Units |
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Super Harvard Architecture—Four Independent Buses |
480 MFLOPS Peak and 320 MFLOPS Sustained |
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for Dual Data Fetch, Instruction Fetch, and |
Performance (Based on FIR) |
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Nonintrusive, Zero-Overhead I/O |
Dual Data Address Generators (DAGs) with Modulo and |
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Backwards-Compatible—Assembly Source Level |
Bit-Reverse Addressing |
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Compatible with Code for ADSP-2106x DSPs |
Zero-Overhead Looping and Single-Cycle Loop Setup, |
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Single-Instruction-Multiple-Data (SIMD) Computational |
Providing Efficient Program Sequencing |
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Architecture—Two 32-Bit IEEE Floating-Point |
IEEE 1149.1 JTAG Standard Test Access Port and |
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Computation Units, Each with a Multiplier, ALU, |
On-Chip Emulation |
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Shifter, and Register File |
400-Ball 27 27 mm Metric PBGA Package |
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Integrated Peripherals—Integrated I/O Processor, |
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4 M Bit On-Chip Dual-Ported SRAM, Glueless |
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Multiprocessing Features, and Ports (Serial, Link, |
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External Bus, and JTAG) |
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FUNCTIONAL BLOCK DIAGRAM
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, 2 352&(6625
6
SHARC is a registered trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and |
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reliable. However, no responsibility is assumed by Analog Devices for its |
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use, nor for any infringements of patents or other rights of third parties |
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A. |
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which may result from its use. No license is granted by implication or |
Tel:781/329-4700 |
World Wide Web Site: http://www.analog.com |
otherwise under any patent or patent rights of Analog Devices. |
Fax:781/326-8703 |
© Analog Devices, Inc., 2001 |