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DSP Microcomputer

Preliminary Technical Data

ADSP-2196

ADSP-219x DSP CORE FEATURES

Independent ALU, Multiplier/Accumulator, and Barrel

6.25 ns Instruction Cycle Time (Internal), for up to

Shifter Computational Units with Dual 40-bit

160 MIPS Sustained Performance

Accumulators

ADSP-218x Family Code Compatible with the Same

Single-Cycle Context Switch between Two Sets of

Easy -to-Use Algebraic Syntax

Computational and DAG Registers

Single-Cycle Instruction Execution

Parallel Execution of Computation and Memory

Up to 16M words of Addressable Memory Space with

Instructions

24 Bits of Addressing Width

Pipelined Architecture Supports Efficient Code

Dual Purpose Program Memory for Both Instruction and

Execution at Speeds up to 160 MIPS

Data Storage

Register File Computations with All Nonconditional,

Fully Transparent Instruction Cache Allows Dual

Nonparallel Computational Instructions

Operand Fetches in Every Instruction Cycle

Powerful Program Sequencer Provides Zero-Overhead

Unified Memory Space Permits Flexible Address

Looping and Conditional Instruction Execution

Generation, Using Two Independent DAG Units

Architectural Enhancements for Compiled C

Code Efficiency