ADSP-BF535
SDRAM Interface Timing
For proper SDRAM controller operation, the maximum load capacitance is 50 pF for ADDR, DATA, ABE3–0/SDQM3–0,
CLKOUT/SCLK1, SCLK0, SCKE, SA10, SRAS, SCAS, SWE, and SMS3-0.
Table 16. SDRAM Interface Timing
Parameter |
|
Min |
Max |
Unit |
|
|
|
|
|
Timing Requirements |
|
|
|
|
tSSDAT |
DATA Setup Before SCLK0/SCLK1 |
2.1 |
|
ns |
tHSDAT |
DATA Hold After SCLK0/SCLK1 |
2.8 |
|
ns |
Switching Characteristics |
|
|
|
|
tSCLK |
SCLK0/SCLK1 Period |
7.5 |
|
ns |
tSCLKH |
SCLK0/SCLK1 Width High |
2.5 |
|
ns |
tSCLKL |
SCLK0/SCLK1 Width Low |
2.5 |
|
ns |
tDCAD |
Command, ADDR, Data Delay After SCLK0/SCLK11 |
|
6.0 |
ns |
tHCAD |
Command, ADDR, Data Hold After SCLK0/SCLK11 |
0.8 |
|
ns |
tDSDAT |
Data Disable After SCLK0/SCLK1 |
|
6.0 |
ns |
tENSDAT |
Data Enable After SCLK0/SCLK1 |
1.0 |
|
ns |
1 Command pins include: SRAS, SCAS, SWE, SDQM3–0, SMS, SA10, and SCKE.
|
tSCLK |
tSCLKH |
|
|
|
SCLK0/ |
|
|
SCLK1 |
|
|
tSSDAT |
tHSDAT |
tSCLKL |
|
||
DATA |
|
|
(IN) |
|
tDSDAT |
tDCAD |
|
|
tENSDAT |
|
tHCAD |
DATA |
|
|
(OUT) |
|
|
tDCAD |
|
|
CMND1 |
|
|
ADDR |
|
|
(OUT) |
|
|
|
|
tHCAD |
NOTE 1: COMMAND = SRAS, SCAS, SWE, SDQM3–0, SMS, SA10, AND SCKE.
Figure 13. SDRAM Interface Timing
REV. A |
–29– |