Serial Peripheral Interface (SPI) Port —Master Timing

Parameter

Min

Max

Unit

Timing Requirements

tSSPID

Data Input Valid to SCK Edge (Data Input Setup)

6.5

ns

tHSPID

SCK Sampling Edge to Data Input Invalid

1.6

ns

Switching Characteristics

tSDSCIM

SPIxSEL Low to First SCK Edge (x=0 or 1)

(2 tSCLK) – 3

ns

tSPICHM

Serial Clock High Period

(2 tSCLK) – 3

ns

tSPICLM

Serial Clock Low Period

(2 tSCLK) – 3

ns

tSPICLK

Serial Clock Period

4 tSCLK

ns

tHDSM

Last SCK Edge to SPIxSEL High (x=0 or 1)

(2 tSCLK) – 3

ns

tSPITDM

Sequential Transfer Delay

2 tSCLK

ns

tDDSPID

SCK Edge to Data Out Valid (Data Out Delay)

0.0

6.0

ns

tHDSPID

SCK Edge to Data Out Invalid (Data Out Hold)

0.0

5.0

ns

SPIxSEL

(OUTPUT)

(x = 0 OR 1)

SCK

tS D S C IM

tS P I C H M

tS P IC LM

tS P I C LK

tH D S M

tS P IT D M

(CPOL = 0)

(OUTPUT)

SCK

tS P IC L M

tSP I C H M

(CPOL = 1)

(OUTPUT)

tD D S P I D

tH D S P ID

MOSI

MSB

LSB

(OUTPUT)

tS S P ID

CPHA = 1

tS S P I D

tH S P I D

tH S P I D

MISO

MSB

LSB

(INPUT)

VALID

VALID

tD D S P I D

tH D S P I D

MOSI

MSB

LSB

(OUTPUT)

CPHA = 0

tS S P I D

tH S P ID