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ADSP-BF535
Programmable Flags Cycle Timing
Table 12 and Figure 9 describe programmable flag operations.
Table 12. Programmable Flags Cycle Timing
Parameter |
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Min |
Max |
Unit |
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Timing Requirements |
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tHFIES |
Edge Sensitive Flag Input Hold is Asynchronous |
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3.0 |
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ns |
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tHFILS |
Level Sensitive Flag Input Hold |
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tSCLK+3 |
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ns |
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Switching Characteristics |
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tDFO |
Flag Output Delay with Respect to SCLK |
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6.0 |
ns |
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tHFO |
Flag Output Hold After SCLK High |
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6.0 |
ns |
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SCLK |
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tDFO |
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tHFO |
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PF (OUTPUT) |
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FLAG |
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OUTPUT |
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tHFIxS
PF (INPUT)
FLAG INPUT
Figure 9. Programmable Flags Cycle Timing
REV. A |
–25– |