TIMING SPECIFICATIONS

Table 9 and Table 10 describe the timing requirements for the

operating frequencies, as described in Absolute Maximum

ADSP-BF535 Blackfin processor clocks. Take care in selecting

Ratings on Page 22. Table 10 describes phase-locked loop

MSEL and SSEL ratios so as not to exceed the maximum core

operating conditions.

clock, system clock and Voltage Controlled Oscillator (VCO)

Table 9. Core Clock Requirements

Parameter

Min

Max

Unit

tCCLK1.6

Core Cycle Period (VDDINT =1.6 V–50 mV)

2.86

200

ns

tCCLK1.5

Core Cycle Period (VDDINT =1.5 V–5%)

3.33

200

ns

tCCLK1.4

Core Cycle Period (VDDINT =1.4 V–5%)

3.70

200

ns

tCCLK1.3

Core Cycle Period (VDDINT =1.3 V–5%)

4.17

200

ns

tCCLK1.2

Core Cycle Period (VDDINT =1.2 V–5%)

4.76

200

ns

tCCLK1.1

Core Cycle Period (VDDINT =1.1 V–5%)

5.56

200

ns

tCCLK1.0

Core Cycle Period (VDDINT =1.0 V–5%)

6.67

200

ns

Table 10. Phase-Locked Loop Operating Conditions

Parameter

Min

Nominal

Max

Unit

Operating Voltage

1.425

1.5

1.575

V

Jitter, Rising Edge to Rising Edge, Per Output1

120

ps

Jitter, Rising Edge to Falling Edge, Per Output1

60

ps

Skew, Rising Edge to Rising Edge, Any Two Outputs1

120

ps

Voltage Controlled Oscillator (VCO) Frequency1

40

400

MHz

VDDPLL Induced Jitter1

1

ps/mV

REV. A

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