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Analog and Mixed-signal Extensions to Verilog HDL

Version 2.3.1, June 1, 2009

9.5.8 Detecting EOF

For example:

integer code;

code = $feof ( fd );

returns a nonzero value when EOF has previously been detected reading the input file fd. It returns zero otherwise.

9.5.9 Behavior of the file I/O tasks in the analog block during iterative solving

If a file is being read from during an iterative solve and if that iteration is rejected, then the file pointer is reset to the file position that it pointed to before the iterative solve started.

If a file is being written to during an iterative solve, then the file write operations shall not be performed unless the iteration is accepted. The exception to this is the $fdebug. If $fdebug is evaluated during an iteration, the write operation shall occur even if the evaluation occurred during an iteration that was rejected.

The features of the underlying implementation of file I/O on the host system may prevent the file position being reset after an iteration is rejected. In this case, a fatal error will be reported.

9.6 Timescale system tasks

Verilog AMS HDL does not extend the timescale tasks defined in IEEE std 1364-2005 Verilog HDL.

9.7 Simulation control system tasks

Verilog AMS HDL extends the two simulation control tasks, $finish and $stop so that they can be run in the analog context.

This section describes their behavior if used in the analog context.

Verilog AMS HDL also supports three new simulation control tasks in the analog context only; $fatal, $error, $warning.

9.7.1 $finish

The syntax for this task is shown in Syntax 9-5.

finish_task ::= $finish [ ( n ) ] ;

Syntax 9-5—Syntax for the finish_task

If $finish is called during an accepted iteration, then the simulator shall exit after the current solution is complete. $finish called during a rejected iteration shall have no effect.


Copyright © 2009 Accellera Organization, Inc. All rights reserved.



Version 2.3.1, June 1, 2009


If an expression is supplied to this task, its value determines which diagnostic messages are printed after the $finish call is executed, as shown in Table 9-24. One (1) is the default if no argument is supplied.


Table 9-24—Diagnostic messages








Prints nothing




Prints simulation time and location




Prints simulation time, location, and statistics about the memory and CPU time used in simulation



9.7.2 $stop

The syntax for this task is shown in Syntax 9-6.

stop_task ::=

$stop [ ( n ) ] ;

Syntax 9-6—Syntax for the stop_task

A call to $stop during an accepted iteration causes simulation to be suspended at a converged timepoint. This task takes an optional expression argument (0, 1, or 2), which determines what type of diagnostic message is printed. The amount of diagnostic messages output increases with the value of n, as shown in Table 9-24.

The mechanism for resuming simulation is left to the implementation.

9.7.3 $fatal, $error, $warning, and $info

The syntax form for the severity system task is as follows:

assert_severity_task ::= fatal_message_task

| nonfatal_message_task

fatal_message_task ::= $fatal [ ( finish_number [ , message_argument { , message_argument } ] ) ] ; nonfatal_message_task ::= severity_task [ ( [ message_argument { , message_argument] } ] ) ] ; severity_task ::= $error | $warning | $info

finish_number ::= 0 | 1 | 2

Syntax 9-7—Assertion severity tasks

The behavior of assert severity tasks is as follows:

$fatal shall generate a run-time fatal assertion error, which terminates the simulation with an errorcode. The first argument passed to $fatal shall be consistent with the corresponding argument to the Verilog $finish system task, which sets the level of diagnostic information reported by the tool. Calling $fatal results in an implicit call to $finish.

$error shall be a run-time error.

$warning shall be a run-time warning, which can be suppressed in a tool-specific manner.

Copyright © 2009 Accellera Organization, Inc.


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