9.21 Connectmodule driver access system functions and operator

Verilog-AMS HDL extends IEEE std 1364-2005 Verilog HDL with a set of driver access functions. Ver- ilog-AMS HDL also adds a new operator, driver_update that is used in combination with the driver access functions which is described here for that reason.

Access to individual drivers and net resolution is necessary for accurate implementation of connect modules (see 7.5). A driver of a signal is a process which assigns a value to the signal, or a connection of the signal to an output port of a module instance or simulation primitive.

The driver access functions described here only access drivers found in ordinary modules and not to those found in connect modules. Driver access functions can only be called from connect modules.

A signal can have any number of drivers; for each driver the current status, value, and strength can be accessed.

9.21.1 $driver_count

$driver_count returns an integer representing the number of drivers associated with the signal in question. The syntax is shown in Syntax 9-16.

driver_count_function ::= $driver_count ( signal_name )

Syntax 9-16—Syntax for $driver_count

The drivers are arbitrarily numbered from 0 to N-1, where N is the total number of ordinary drivers contributing to the signal value. For example, if this function returns a value 5 then the signal has five drivers numbered from 0 to 4.

9.21.2 $driver_state

driver_state returns the current value contribution of a specific driver to the state of the signal. The syntax is shown in Syntax 9-17.

driver_state_function ::=

$driver_state ( signal_name , driver_index )

Syntax 9-17—Syntax for $driver_state

driver_index is an integer value between 0 and N-1, where N is the total number of drivers contributing to the signal value. The state value is returned as 0, 1, x, or z.

9.21.3 $driver_strength

driver_strength returns the current strength contribution of a specific driver to the strength of the signal. The syntax is shown in Syntax 9-18.

driver_strength_function ::=

$driver_strength ( signal_name , driver_index )

Syntax 9-18—Syntax for $driver_strength

driver_index is an integer value between 0 and N-1, where N is the total number of drivers contributing to the signal value. The strength value is returned as two strengths, Bits 5-3 for strength0 and Bits 2-0 for strength1 (see IEEE std 1364-2005 Verilog HDL, subclauses 7.10 and 7.11).

If the value returned is 0 or 1, strength0 returns the high-end of the strength range and strength1 returns the low-end of the strength range. Otherwise, the strengths of both strength0 and strength1 is defined as shown in Figure 9-3 below.

Figure 9-3: Strength value mapping

9.21.4 driver_update

The status of drivers for a given signal can be monitored with the event detection keyword driver_update. It can be used in conjunction with the event detection operator @ to detect updates to any of the drivers of the signal.

Example:

always @(driver_update clock) statement;

causes the statement to execute any time a driver of the signal clock is updated. Here, an update is defined as the addition of a new pending value to the driver. This is true whether or not there is a change in the resolved value of the signal.

9.21.5 Receiver net resolution

As a result of driver receiver segregation, the drivers and receivers are separated so that any analog connected to a mixed net has the opportunity to influence the value driving the digital receivers. Since a single digital port is used in the connect module, the user must specify the value that the receivers will see. By not specifying the receiver value directly in the connect module driver, receiver segregation will be ignored, which is the default case. This assignment of the receiver value is done via the assign statement in which the digital port will be used to read the driver values as well as to set the receiver value.

1)The default is equivalent of assign d_receivers = d_drivers ;

Where the value passed to the receivers through driver receiver segregation is the value being driven without delay or any impact from analog connections to the net. This is essentially bypassing driver receiver segregation.

2)Anything else is done explicitly, such as:

reg out; // value of out determined in CM, see example in 9.21.6 assign d = out;

In this case, the digital port of the connect module will drive the receivers with a value determined in the connect module. This value may potentially be different from the value of the drivers of the connect module digital port.

9.21.6 Connect module example using driver access functions

Using the example shown in Figure 9-4, a connect module can be created using driver access functions to accurately model the effects of multiple drivers on an interface.

c1

Figure 9-4: Driver-receiver segregation connect module example

The connect module below takes advantage of much of the mixed-signal language including driver access functions. This module effectively adds another parallel resistor from output to ground whenever a digital output connected to the net goes high, and another parallel resistor from output to rail (supply) whenever a digital output connected to the net goes low. If this is used as the connect module in Figure 9-4, not only is the delay from digital outputs to the digital input a function of the value of the capacitor, for a given capacitance it takes approximately half the time (since two gates are driving the signal rather than one).

connectmodule c2e(d,a); input d;

output a;

ddiscrete d;

electrical a, rail, gnd;

reg out; ground gnd;

branch (rail,a)pull_up; branch (a,gnd)pull_down; branch (rail,gnd)power;

parameter real impedance0 = 120.0; parameter real impedance1 = 100.0; parameter real impedanceOff = 1e6; parameter real vt_hi = 3.5; parameter real vt_lo = 1.5; parameter real supply = 5.0;